gateware: core/platform: Updated PLL settings to use correct input cl…

…ock, and fixed typo in the PLL module
squishy-scsi · Oct 3, 2024 · 6648e67 · 6648e67
1 parent 775ee26
commit 6648e67
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/squishy/gateware/core/pll.py b/squishy/gateware/core/pll.py
@@ -98,7 +98,7 @@ def elaborate(self, platform) -> Module:
 
 			o_CLKOP   = pll_clk,
 			i_CLKFB   = pll_clk,
-			i_ENCLKOP = Const(1),
+			i_ENCLKOP = Const(0),
 			o_LOCK    = self.pll_locked,
 
 			i_RST       = Const(0),

diff --git a/squishy/gateware/platform/rev2.py b/squishy/gateware/platform/rev2.py
@@ -53,14 +53,14 @@ class SquishyRev2(SquishyPlatform, ECP5Platform):
 
 	clock_domain_generator = ECP5ClockDomainGenerator
 
-	# generated with `ecppll -i 16 -o 400 -f /dev/stdout`
+	# generated with `ecppll -i 100 -o 400 -f /dev/stdout`
 	pll_config = {
 		'freq'     : 4e8,
-		'ifreq'    : 16,
+		'ifreq'    : 100,
 		'ofreq'    : 400,
 		'clki_div' : 1,
 		'clkop_div': 1,
-		'clkfb_div': 25,
+		'clkfb_div': 4,
 	}
 
 	flash = {