Merge supervisor firmware tree into mainline #42
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…ing embedded code, I swear.
… they're needed by other things and can't always be inlined. Also had to tell GCC to *not* replace the implementation of these functions with calls to them, because we are, in fact, the implementation of said calls, thanks GCC
…re-link if it changes
…rgs to the linker also gets them
…slation units, seizing the means of production
…d pin needed pin initialization to `setup_io`
…rs, and disambiguated the names
…ing into an SPI specific implementation. Also, set up the framework for reading and writing from the on-board configuration flash, along with validating the link by checking the ID
This is due to the fact that the ARM Cortex-M0+ does not have any atomic instructions, and we're not able to link against any stdlibs, ***AND*** libatomic isn't even included with the compiler for this platform anyway.
… for things for a set amount of time
…from a span of bytes
…should have been done
…ove it in line with the other naming conventions
… entries causing the SysTick handler to be in the wrong spot, i'm surprised anything worked
… to be in config mode (with the appropriate delay)
…FLASH into the FPGA
… would have caused due to calling a naked function
…to set the LEDs to a known state
…lash and FPGA id failure, relying on just the new fault system
…ning despite other interrupts to ensure when we hit the fault handler we can still blink out an error code
…n't do a full JEDEC compliant ID read, only enough for our onboard flash
…e extra whitespace
… to the PSRAM from the firmware end
…we brown-out rather than lose all power causing the peripherals to stay configured causing a lockup state on power on from reset
…at least there now
…ermine if we're restarting due to a brownout or not
…ng the core if we browned out
…n advanced address after read for later use
…tstream loading from PSRAM to FPGA
…m out of the PSRAM
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