Fix overlap test failing when port ids are not correctly added to trace, add regression test case

lib/add-start-and-end-port-ids-if-missing.ts

@@ -0,0 +1,43 @@
+import type {
+  PCBPort,
+  PCBTrace,
+  SourceTrace,
+  AnySoupElement,
+  PCBTraceError,
+} from "@tscircuit/soup"
+
+function distance(x1: number, y1: number, x2: number, y2: number): number {
+  return Math.sqrt((x2 - x1) ** 2 + (y2 - y1) ** 2)
+}
+
+export const addStartAndEndPortIdsIfMissing = (
+  soup: AnySoupElement[],
+): void => {
+  const pcbPorts: PCBPort[] = soup.filter((item) => item.type === "pcb_port")
+  const pcbTraces: PCBTrace[] = soup.filter((item) => item.type === "pcb_trace")
+
+  // Add start_pcb_port_id and end_pcb_port_id if not present
+  for (const trace of pcbTraces) {
+    for (let index = 0; index < trace.route.length; index++) {
+      const segment = trace.route[index]
+      if (segment.route_type === "wire") {
+        if (!segment.start_pcb_port_id && index === 0) {
+          const startPort = pcbPorts.find(
+            (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,
+          )
+          if (startPort) {
+            segment.start_pcb_port_id = startPort.pcb_port_id
+          }
+        }
+        if (!segment.end_pcb_port_id && index === trace.route.length - 1) {
+          const endPort = pcbPorts.find(
+            (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,
+          )
+          if (endPort) {
+            segment.end_pcb_port_id = endPort.pcb_port_id
+          }
+        }
+      }
+    }
+  }
+}

lib/check-each-pcb-port-connected.ts

@@ -5,47 +5,21 @@ import type {
   AnySoupElement,
   PCBTraceError,
 } from "@tscircuit/soup"
-
-function distance(x1: number, y1: number, x2: number, y2: number): number {
-  return Math.sqrt(Math.pow(x2 - x1, 2) + Math.pow(y2 - y1, 2))
-}
+import { addStartAndEndPortIdsIfMissing } from "./add-start-and-end-port-ids-if-missing"
 
 function checkEachPcbPortConnected(soup: AnySoupElement[]): PCBTraceError[] {
+  addStartAndEndPortIdsIfMissing(soup)
   const pcbPorts: PCBPort[] = soup.filter((item) => item.type === "pcb_port")
   const pcbTraces: PCBTrace[] = soup.filter((item) => item.type === "pcb_trace")
   const sourceTraces: SourceTrace[] = soup.filter(
     (item) => item.type === "source_trace",
   )
   const errors: PCBTraceError[] = []
 
-  // Add start_pcb_port_id and end_pcb_port_id if not present
-  pcbTraces.forEach((trace) => {
-    trace.route.forEach((segment, index) => {
-      if (segment.route_type === "wire") {
-        if (!segment.start_pcb_port_id && index === 0) {
-          const startPort = pcbPorts.find(
-            (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,
-          )
-          if (startPort) {
-            segment.start_pcb_port_id = startPort.pcb_port_id
-          }
-        }
-        if (!segment.end_pcb_port_id && index === trace.route.length - 1) {
-          const endPort = pcbPorts.find(
-            (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,
-          )
-          if (endPort) {
-            segment.end_pcb_port_id = endPort.pcb_port_id
-          }
-        }
-      }
-    })
-  })
-
   for (const port of pcbPorts) {
     const connectedTraces = pcbTraces.filter((trace) =>
       trace.route.some(
-        (segment) =>
+        (segment: any) =>
           segment.route_type === "wire" &&
           (segment.start_pcb_port_id === port.pcb_port_id ||
             segment.end_pcb_port_id === port.pcb_port_id),

lib/check-each-pcb-trace-non-overlapping.ts

@@ -5,6 +5,10 @@ import type {
   PCBTraceError,
 } from "@tscircuit/soup"
 import { NetManager } from "./net-manager"
+import { addStartAndEndPortIdsIfMissing } from "./add-start-and-end-port-ids-if-missing"
+import Debug from "debug"
+
+const debug = Debug("tscircuit:checks:check-each-pcb-trace-non-overlapping")
 
 /**
  * Checks if lines given by (x1, y1) and (x2, y2) intersect with line
@@ -42,8 +46,9 @@ function tracesOverlap(trace1: PCBTrace, trace2: PCBTrace): boolean {
         seg2.route_type === "wire" &&
         seg3.route_type === "wire" &&
         seg4.route_type === "wire" &&
-        seg1.layer === seg3.layer &&
-        lineIntersects(
+        seg1.layer === seg3.layer
+      ) {
+        const areLinesIntersecting = lineIntersects(
           seg1.x,
           seg1.y,
           seg2.x,
@@ -53,8 +58,7 @@ function tracesOverlap(trace1: PCBTrace, trace2: PCBTrace): boolean {
           seg4.x,
           seg4.y,
         )
-      ) {
-        return true
+        return areLinesIntersecting
       }
     }
   }
@@ -141,16 +145,17 @@ function getPortIdsConnectedToTrace(trace: PCBTrace) {
 function getPortIdsConnectedToTraces(...traces: PCBTrace[]) {
   const connectedPorts = new Set<string>()
   for (const trace of traces) {
-    getPortIdsConnectedToTrace(trace).forEach((portId) =>
-      connectedPorts.add(portId),
-    )
+    for (const portId of getPortIdsConnectedToTrace(trace)) {
+      connectedPorts.add(portId)
+    }
   }
   return Array.from(connectedPorts)
 }
 
 function checkEachPcbTraceNonOverlapping(
   soup: AnySoupElement[],
 ): PCBTraceError[] {
+  addStartAndEndPortIdsIfMissing(soup)
   const pcbTraces: PCBTrace[] = soup.filter(
     (item): item is PCBTrace => item.type === "pcb_trace",
   )
@@ -161,12 +166,18 @@ function checkEachPcbTraceNonOverlapping(
   const netManager = new NetManager()
 
   // TODO use source port ids instead of port ids, parse source ports for connections
-  pcbTraces.forEach((trace) =>
-    netManager.setConnected(getPortIdsConnectedToTrace(trace)),
-  )
+  for (const trace of pcbTraces) {
+    netManager.setConnected(getPortIdsConnectedToTrace(trace))
+  }
 
   for (let i = 0; i < pcbTraces.length; i++) {
     for (let j = i + 1; j < pcbTraces.length; j++) {
+      debug(
+        `Checking overlap for ${pcbTraces[i].pcb_trace_id} and ${pcbTraces[j].pcb_trace_id}`,
+      )
+      debug(
+        `Connected ports: ${getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j])}`,
+      )
       if (
         netManager.isConnected(
           getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j]),

package.json

@@ -18,6 +18,8 @@
     "@tscircuit/soup": "^0.0.40",
     "@tscircuit/soup-util": "^0.0.13",
     "@types/bun": "latest",
+    "@types/debug": "^4.1.12",
+    "debug": "^4.3.5",
     "tsup": "^8.2.3"
   },
   "peerDependencies": {