Skip to content
View ultraembedded's full-sized avatar
  • UK

Block or report ultraembedded

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. biriscv biriscv Public

    32-bit Superscalar RISC-V CPU

    Verilog 865 146

  2. riscv riscv Public

    RISC-V CPU Core (RV32IM)

    Verilog 1.3k 235

  3. cores cores Public

    Various HDL (Verilog) IP Cores

    Verilog 709 215

  4. riscv_soc riscv_soc Public

    Basic RISC-V Test SoC

    Verilog 104 29

  5. FPGAmp FPGAmp Public

    720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

    C 268 43

  6. exactstep exactstep Public

    Instruction set simulator for RISC-V, MIPS and ARM-v6m

    C++ 89 17