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armv6m.cpp
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armv6m.cpp
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#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <assert.h>
#include "armv6m.h"
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
#define DPRINTF(l,a) do { if (m_trace & l) printf a; } while (0)
#define TRACE_ENABLED(l) (m_trace & l)
//-----------------------------------------------------------------
// Constructor
//-----------------------------------------------------------------
Armv6m::Armv6m(uint32_t baseAddr /*= 0*/, uint32_t len /*= 0*/)
{
m_mem_regions = 0;
m_has_breakpoints = false;
m_step_cb = NULL;
// Some memory defined
if (len != 0)
create_memory(baseAddr, len);
reset(baseAddr);
// SysTick Peripheral
m_systick = new Systick(0xE000E010, 0);
attach_memory(m_systick, 0xE000E010, 32);
// Simple UART - writes to 0xE0000000 are output on the console
attach_memory(new Sysuart(0xE0000000, 0), 0xE0000000, 4);
// Dummy System Control Block - writes have no effect, reads return 0
attach_memory(new DummyDevice(0xE000ED00), 0xE000ED00, 36);
}
//-----------------------------------------------------------------
// Deconstructor
//-----------------------------------------------------------------
Armv6m::~Armv6m()
{
for (int m=0;m<m_mem_regions;m++)
{
if (m_mem[m])
delete m_mem[m];
m_mem[m] = NULL;
}
}
//-----------------------------------------------------------------
// error: Handle an error
//-----------------------------------------------------------------
bool Armv6m::error(bool terminal, const char *fmt, ...)
{
va_list args;
va_start(args, fmt);
vprintf(fmt, args);
va_end(args);
exit(-1);
return true;
}
//-----------------------------------------------------------------
// create_memory: Create a memory region
//-----------------------------------------------------------------
bool Armv6m::create_memory(uint32_t baseAddr, uint32_t len, uint8_t *buf /*=NULL*/)
{
if (buf)
return attach_memory(new SimpleMemory(buf, len), baseAddr, len);
else
return attach_memory(new SimpleMemory(len), baseAddr, len);
}
//-----------------------------------------------------------------
// attach_memory: Attach a memory device to a particular region
//-----------------------------------------------------------------
bool Armv6m::attach_memory(Memory *memory, uint32_t baseAddr, uint32_t len)
{
if (m_mem_regions < MAX_MEM_REGIONS)
{
m_mem_base[m_mem_regions] = baseAddr;
m_mem_size[m_mem_regions] = len;
m_mem[m_mem_regions] = memory;
m_mem[m_mem_regions]->reset();
m_mem_regions++;
return true;
}
return false;
}
//-----------------------------------------------------------------
// set_pc: Set PC
//-----------------------------------------------------------------
void Armv6m::set_pc(uint32_t pc)
{
m_regfile[REG_PC] = pc;
}
//-----------------------------------------------------------------
// set_register: Set register value
//-----------------------------------------------------------------
void Armv6m::set_register(int r, uint32_t val)
{
if (r < REGISTERS)
m_regfile[r] = val;
}
//-----------------------------------------------------------------
// get_register: Get register value
//-----------------------------------------------------------------
uint32_t Armv6m::get_register(int r)
{
if (r < REGISTERS)
return m_regfile[r];
return 0;
}
//-----------------------------------------------------------------
// set_flag: Adjust flag fields
//-----------------------------------------------------------------
void Armv6m::set_flag(uint32_t flag, bool val)
{
if (val)
m_apsr |= flag;
else
m_apsr &= ~flag;
}
//-----------------------------------------------------------------
// get_flag: Get particular flag
//-----------------------------------------------------------------
bool Armv6m::get_flag(uint32_t flag)
{
return (m_apsr & flag) != 0;
}
//-----------------------------------------------------------------
// get_break: Get breakpoint status (and clear)
//-----------------------------------------------------------------
bool Armv6m::get_break(void)
{
bool brk = m_break;
m_break = false;
return brk;
}
//-----------------------------------------------------------------
// set_breakpoint: Set breakpoint on a given PC
//-----------------------------------------------------------------
bool Armv6m::set_breakpoint(uint32_t pc)
{
m_breakpoints.push_back(pc);
m_has_breakpoints = true;
return true;
}
//-----------------------------------------------------------------
// set_breakpoint: Clear breakpoint on a given PC
//-----------------------------------------------------------------
bool Armv6m::clr_breakpoint(uint32_t pc)
{
for (std::vector<uint32_t>::iterator it = m_breakpoints.begin() ; it != m_breakpoints.end(); ++it)
if ((*it) == pc)
{
m_breakpoints.erase(it);
m_has_breakpoints = !m_breakpoints.empty();
return true;
}
return false;
}
//-----------------------------------------------------------------
// check_breakpoint: Check if breakpoint has been hit
//-----------------------------------------------------------------
bool Armv6m::check_breakpoint(uint32_t pc)
{
for (std::vector<uint32_t>::iterator it = m_breakpoints.begin() ; it != m_breakpoints.end(); ++it)
if ((*it) == pc)
return true;
return false;
}
//-----------------------------------------------------------------
// reset: Reset CPU state
//-----------------------------------------------------------------
void Armv6m::reset(uint32_t start_addr)
{
m_fault = false;
m_break = false;
m_trace = 0;
for (int i=0;i<REGISTERS;i++)
m_regfile[i] = 0;
m_apsr = 0;
m_entry_point = start_addr;
// Fetch SP & boot PC from vector table
m_regfile[REG_SP] = read32(m_entry_point);
m_regfile[REG_LR] = 0;
m_regfile[REG_PC] = read32(m_entry_point + 4) & ~1;
// Start in thread mode with main stack selected
m_msp = m_regfile[REG_SP];
m_psp = 0;
m_current_mode = MODE_THREAD;
m_control = 0; // (SPSEL = 0, nPRIV = 0)
m_primask = 0;
// Misc
m_ipsr = 0;
m_epsr = 0;
}
//-----------------------------------------------------------------
// valid_addr: Check if the physical memory address is valid
//-----------------------------------------------------------------
bool Armv6m::valid_addr(uint32_t address)
{
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
return true;
return false;
}
//-----------------------------------------------------------------
// write: Write a byte to memory (physical address)
//-----------------------------------------------------------------
void Armv6m::write(uint32_t address, uint8_t data)
{
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
{
m_mem[j]->store(address - m_mem_base[j], data, 1);
return ;
}
error(false, "Failed store @ 0x%08x\n", address);
}
//-----------------------------------------------------------------
// write32: Write a word to memory
//-----------------------------------------------------------------
void Armv6m::write32(uint32_t address, uint32_t data)
{
DPRINTF(LOG_MEM, ("MEM: Write32 %x = %x\n", address, data));
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
{
m_mem[j]->store(address - m_mem_base[j], data, 4);
return ;
}
error(false, "Failed store @ 0x%08x\n", address);
}
//-----------------------------------------------------------------
// write_mem: Write to memory
//-----------------------------------------------------------------
void Armv6m::write_mem(uint32_t address, uint32_t data, int width)
{
DPRINTF(LOG_MEM, ("MEM: Write32 %x = %x (width %d)\n", address, data, width));
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
{
m_mem[j]->store(address - m_mem_base[j], data, width);
return ;
}
error(false, "Failed store @ 0x%08x\n", address);
}
//-----------------------------------------------------------------
// read_mem: Read a word from memory
//-----------------------------------------------------------------
uint32_t Armv6m::read_mem(uint32_t address, int width)
{
if (width == 4)
address &= ~3;
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
return m_mem[j]->load(address - m_mem_base[j], width, false);
return 0;
}
//-----------------------------------------------------------------
// read: Read a byte from memory (physical address)
//-----------------------------------------------------------------
uint8_t Armv6m::read(uint32_t address)
{
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
return m_mem[j]->load(address - m_mem_base[j], 1, false);
return 0;
}
//-----------------------------------------------------------------
// read32: Read a word from memory (physical address)
//-----------------------------------------------------------------
uint32_t Armv6m::read32(uint32_t address)
{
address &= ~3;
for (int j=0;j<m_mem_regions;j++)
if (address >= m_mem_base[j] && address < (m_mem_base[j] + m_mem_size[j]))
{
uint32_t data = m_mem[j]->load(address - m_mem_base[j], 4, false);
DPRINTF(LOG_MEM, ("MEM: Read32 %08x = %08x\n", address, data));
return data;
}
return 0;
}
//-----------------------------------------------------------------
// get_opcode: Get instruction from address
//-----------------------------------------------------------------
uint32_t Armv6m::get_opcode(uint32_t address)
{
return read32(address);
}
//-----------------------------------------------------------------
// step: Step through one instruction
//-----------------------------------------------------------------
void Armv6m::step(void)
{
uint16_t inst;
uint16_t inst2;
int inst_32_bit;
// EXC_RETURN value in PC
if ((m_regfile[REG_PC] & EXC_RETURN) == EXC_RETURN)
armv6m_exc_return(m_regfile[REG_PC]);
// Fetch
inst = armv6m_read_inst(m_regfile[REG_PC]);
// Decode
inst_32_bit = armv6m_decode(inst);
// [32-bit instruction] Fetch another half word
if (inst_32_bit)
inst2 = armv6m_read_inst(m_regfile[REG_PC]+2);
else
inst2 = 0;
DPRINTF(LOG_FETCH, ("%08X: 0x%04X \n",m_regfile[REG_PC],inst));
if (TRACE_ENABLED(LOG_INST))
armv6m_dump_inst(inst);
// Execute
armv6m_execute(inst, inst2);
if (TRACE_ENABLED(LOG_REGISTERS))
{
int i;
for (i=0;i<REGISTERS;i+=4)
{
printf("%d: ", i);
if (i == 12)
printf("%08x %08x\n", m_regfile[i+0], m_regfile[i+1]);
else
printf("%08x %08x %08x %08x\n", m_regfile[i+0], m_regfile[i+1], m_regfile[i+2], m_regfile[i+3]);
}
printf("Flags = %c%c%c%c\n", m_apsr & APSR_N ? 'N':'-',
m_apsr & APSR_Z ? 'Z':'-',
m_apsr & APSR_C ? 'C':'-',
m_apsr & APSR_V ? 'V':'-');
}
if (TRACE_ENABLED(LOG_FLAGS))
{
static uint32_t old_apsr = 0;
if (m_apsr != old_apsr)
{
printf("%08X: Flags = %c%c%c%c\n", m_regfile[REG_PC],
m_apsr & APSR_N ? 'N':'-',
m_apsr & APSR_Z ? 'Z':'-',
m_apsr & APSR_C ? 'C':'-',
m_apsr & APSR_V ? 'V':'-');
old_apsr = m_apsr;
}
}
// Systick
static bool systick_irq = false;
if (m_systick->clock() != -1)
systick_irq = true;
// TODO: Verify likely to be incorrect...
if (systick_irq && (m_current_mode == MODE_THREAD) && !(m_primask & PRIMASK_PM))
{
m_regfile[REG_PC] = armv6m_exception(m_regfile[REG_PC], 15);
systick_irq = false;
}
// Dump state
if (TRACE_ENABLED(LOG_REGISTERS))
{
// Register trace
int i;
for (i=0;i<REGISTERS;i+=4)
{
DPRINTF(LOG_REGISTERS,( " %d: ", i));
DPRINTF(LOG_REGISTERS,( " %08x %08x %08x %08x\n", m_regfile[i+0], m_regfile[i+1], m_regfile[i+2], m_regfile[i+3]));
}
}
// Breakpoint hit?
if (m_has_breakpoints && check_breakpoint(get_pc()))
m_break = true;
if (m_step_cb)
m_step_cb(m_step_cb_arg);
}
//-----------------------------------------------------------------
// set_interrupt: Register pending interrupt
//-----------------------------------------------------------------
void Armv6m::set_interrupt(int irq)
{
}
//-------------------------------------------------------------------
// armv6m_read_inst:
//-------------------------------------------------------------------
uint16_t Armv6m::armv6m_read_inst(uint32_t addr)
{
uint32_t val = 0;
if (addr & 0x2)
val = (read32(addr) >> 16) & 0xFFFF;
else
val = (read32(addr) >> 0) & 0xFFFF;
return val;
}
//-------------------------------------------------------------------
// armv6m_update_sp:
//-------------------------------------------------------------------
void Armv6m::armv6m_update_sp(uint32_t sp)
{
m_regfile[REG_SP] = sp;
// Update shadow stack pointer (depending on mode)
if ((m_control & CONTROL_SPSEL) && (m_current_mode == MODE_THREAD))
m_psp = sp;
else
m_msp = sp;
}
//-------------------------------------------------------------------
// armv6m_update_n_z_flags:
//-------------------------------------------------------------------
void Armv6m::armv6m_update_n_z_flags(uint32_t rd)
{
// Zero
if (rd == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
// Negative
if (rd & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
}
//-------------------------------------------------------------------
// armv6m_add_with_carry:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_add_with_carry(uint32_t rn, uint32_t rm, uint32_t carry_in, uint32_t mask)
{
uint32_t res;
// Perform addition
res = rn + rm + carry_in;
// Zero
if (mask & APSR_Z)
{
if ((res & 0xFFFFFFFF) == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
}
// Negative
if (mask & APSR_N)
{
if (res & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
}
// Carry
if (mask & APSR_C)
{
uint64_t unsigned_sum = (uint64_t)rn + (uint64_t)rm + carry_in;
if (unsigned_sum == (uint64_t)res)
m_apsr &=~APSR_C;
else
m_apsr |= APSR_C;
}
// Overflow
if (mask & APSR_V)
{
int64_t signed_sum = (int64_t)(int32_t)rn + (int64_t)(int32_t)rm + carry_in;
if (signed_sum == (int64_t)(int32_t)res)
m_apsr &=~APSR_V;
else
m_apsr |= APSR_V;
}
return (uint32_t)res;
}
//-------------------------------------------------------------------
// armv6m_shift_left:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_shift_left(uint32_t val, uint32_t shift, uint32_t mask)
{
uint64_t res = val;
res <<= shift;
// Carry Out (res[32])
if (mask & APSR_C)
{
if (res & ((uint64_t)1 << 32))
m_apsr |= APSR_C;
else
m_apsr &=~APSR_C;
}
// Zero
if ((res & 0xFFFFFFFF) == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
// Negative
if (res & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
return (uint32_t)res;
}
//-------------------------------------------------------------------
// armv6m_shift_right:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_shift_right(uint32_t val, uint32_t shift, uint32_t mask)
{
uint32_t res = (shift >= 32) ? 0 : val;
// Carry Out (val[shift-1])
if ((mask & APSR_C) && (shift > 0))
{
// Last lost bit shifted right
if ((val & (1 << (shift-1))) && (shift <= 32))
m_apsr |= APSR_C;
else
m_apsr &=~APSR_C;
}
res >>= shift;
// Zero
if ((res & 0xFFFFFFFF) == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
// Negative
if (res & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
return res;
}
//-------------------------------------------------------------------
// armv6m_arith_shift_right:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_arith_shift_right(uint32_t val, uint32_t shift, uint32_t mask)
{
signed int res = val;
// Carry Out (val[shift-1])
if ((mask & APSR_C) && (shift > 0))
{
// Last lost bit shifted right
if (val & (1 << (shift-1)))
m_apsr |= APSR_C;
else
m_apsr &=~APSR_C;
}
res >>= shift;
// Zero
if ((res & 0xFFFFFFFF) == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
// Negative
if (res & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
return res;
}
//-------------------------------------------------------------------
// armv6m_rotate_right:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_rotate_right(uint32_t val, uint32_t shift, uint32_t mask)
{
uint32_t res;
if (shift == 0)
res = val;
else
{
shift &= 0x1F;
res = val >> shift;
res |= (val << (32 - shift));
}
// Carry out
if (res & 0x80000000)
m_apsr |= APSR_C;
else
m_apsr &=~APSR_C;
// Zero
if ((res & 0xFFFFFFFF) == 0)
m_apsr |= APSR_Z;
else
m_apsr &=~APSR_Z;
// Negative
if (res & 0x80000000)
m_apsr |=APSR_N;
else
m_apsr &=~APSR_N;
return res;
}
//-------------------------------------------------------------------
// armv6m_sign_extend:
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_sign_extend(uint32_t val, int offset)
{
if(val & (1 << (offset-1)))
val |= (~0) << offset;
else
val &= ~((~0) << offset);
return val;
}
//-------------------------------------------------------------------
// armv6m_dump_inst:
//-------------------------------------------------------------------
void Armv6m::armv6m_dump_inst(uint16_t inst)
{
int i = 0;
while (instr_details[i].desc)
{
if ((inst & instr_details[i].mask) == instr_details[i].opcode)
{
DPRINTF(LOG_INST, (" %x: %s\n", m_regfile[REG_PC], instr_details[i].desc));
break;
}
i++;
}
}
//-------------------------------------------------------------------
// armv6m_exception: Handle exception, push registers to stack &
// adjust operating mode.
//-------------------------------------------------------------------
uint32_t Armv6m::armv6m_exception(uint32_t pc, uint32_t exception)
{
uint32_t sp;
// Retrieve shadow stack pointer (depending on mode)
if ((m_control & CONTROL_SPSEL) && (m_current_mode == MODE_THREAD))
sp = m_psp;
else
sp = m_msp;
// Push frame onto current stack
sp-=4;
write32(sp, m_apsr);
sp-=4;
write32(sp, m_regfile[REG_PC]);
sp-=4;
write32(sp, m_regfile[REG_LR]);
sp-=4;
write32(sp, m_regfile[12]);
sp-=4;
write32(sp, m_regfile[3]);
sp-=4;
write32(sp, m_regfile[2]);
sp-=4;
write32(sp, m_regfile[1]);
sp-=4;
write32(sp, m_regfile[0]);
m_regfile[REG_SP] = sp;
// Record exception
m_ipsr = exception & 0x3F;
// Fetch exception vector address into PC
m_regfile[REG_PC] = read32(m_entry_point + (exception * 4)) & ~1;
// LR = Return to handler mode (recursive interrupt?)
if (m_current_mode == MODE_HANDLER)
m_regfile[REG_LR] = 0xFFFFFFF1;
else
{
// LR = Return to thread mode (with main stack)
if ((m_control & CONTROL_SPSEL) == 0)
m_regfile[REG_LR] = 0xFFFFFFF9;
// LR = Return to thread mode (with process stack)
else
m_regfile[REG_LR] = 0xFFFFFFFD;
}
// Swap to handler mode
m_current_mode = MODE_HANDLER;
// Current stack is now main
m_control &= ~CONTROL_SPSEL;
return m_regfile[REG_PC];
}
//-------------------------------------------------------------------
// armv6m_exc_return: Handle returning from an exception
//-------------------------------------------------------------------
void Armv6m::armv6m_exc_return(uint32_t pc)
{
// Handler (exception) mode
if(m_current_mode != MODE_HANDLER)
return ;
// EXC_RETURN value
if((pc & EXC_RETURN) == EXC_RETURN)
{
uint32_t sp;
// TODO: Should be 0x1F...
switch (pc & 0xF)
{
// Return to handler mode (with main stack)
case 0x1:
m_current_mode = MODE_HANDLER;
m_control &= ~CONTROL_SPSEL;
break;
// Return to thread mode (with main stack)
case 0x9:
m_current_mode = MODE_THREAD;
m_control &= ~CONTROL_SPSEL;
break;
// Return to thread mode (with process stack)
case 0xD:
m_current_mode = MODE_THREAD;
m_control |= CONTROL_SPSEL;
break;
default:
assert(!"Not handled");
break;
}
// Pop exception context
sp = m_regfile[REG_SP];
m_regfile[0] = read32(sp);
sp+=4;
m_regfile[1] = read32(sp);
sp+=4;
m_regfile[2] = read32(sp);
sp+=4;
m_regfile[3] = read32(sp);
sp+=4;
m_regfile[12] = read32(sp);
sp+=4;
m_regfile[REG_LR] = read32(sp);
sp+=4;
m_regfile[REG_PC] = read32(sp);
sp+=4;
m_apsr = read32(sp);
sp+=4;
armv6m_update_sp(sp);
}
}
//-------------------------------------------------------------------
// armv6m_decode: Decode ARMv6m instruction
// Returns:
// 0 = 16-bit instruction, execute
// 1 = 32-bit instruction, fetch next word
//-------------------------------------------------------------------
int Armv6m::armv6m_decode(uint16_t inst)
{
int res = 0;
int v_decoded = 0;
m_rd = 0;
m_rt = 0;
m_rm = 0;
m_rn = 0;
m_imm = 0;
m_reglist = 0;
m_cond = 0;
// Group 0?
if (!v_decoded)
{
v_decoded = 1;
m_inst_group = INST_IGRP0;
switch(inst & INST_IGRP0_MASK)
{
// BCC - BCC <label>
// 1 1 0 1 cond imm8
case INST_BCC_OPCODE:
{
m_cond = (inst >> 8) & 0x0F;
m_imm = (inst >> 0) & 0xFF;
}
break;
default:
v_decoded = 0;
break;
}
}
// Group 1?
if (!v_decoded)
{
v_decoded = 1;
m_inst_group = INST_IGRP1;
switch(inst & INST_IGRP1_MASK)
{
// ADDS - ADDS <Rdn>,#<imm8>
// 0 0 1 1 0 Rdn imm8
case INST_ADDS_1_OPCODE:
// SUBS - SUBS <Rdn>,#<imm8>
// 0 0 1 11 Rdn imm8
case INST_SUBS_1_OPCODE:
{
m_rd = (inst >> 8) & 0x7;
m_rn = m_rd;
m_imm= (inst >> 0) & 0xFF;
}
break;
// ADR - ADR <Rd>,<label>
// 1 0 1 0 0 Rd imm8
case INST_ADR_OPCODE:
// MOVS - MOVS <Rd>,#<imm8>
// 0 0 1 0 0 Rd imm8
case INST_MOVS_OPCODE:
{
m_rd = (inst >> 8) & 0x7;
m_imm= (inst >> 0) & 0xFF;
}
break;
// ASRS - ASRS <Rd>,<Rm>,#<imm5>
// 0 0 0 1 0 imm5 Rm Rd
case INST_ASRS_OPCODE:
// LSLS - LSLS <Rd>,<Rm>,#<imm5>
// 0 0 0 0 0 imm5 Rm Rd
case INST_LSLS_OPCODE:
// LSRS - LSRS <Rd>,<Rm>,#<imm5>
// 0 0 0 0 1 imm5 Rm Rd
case INST_LSRS_OPCODE:
{
m_imm= (inst >> 6) & 0x1F;
m_rm = (inst >> 3) & 0x7;
m_rd = (inst >> 0) & 0x7;
}
break;
// B - B <label>
// 1 1 1 0 0 imm11
case INST_B_OPCODE:
{
m_imm= (inst >> 0) & 0x7FF;
}
break;
// BL - BL <label>
// 1 1 1 01 S imm10 1 1 J1 1 J2 imm11
case INST_BL_OPCODE:
{
// 32-bit instruction
res = 1;
m_imm = (inst >> 0) & 0x7FF;
m_rd = REG_LR; // Implicit
// TODO: Clean this up
// Check next instruction to work out if this is a BL or MSR
if ((armv6m_read_inst(m_regfile[REG_PC]+2) & 0xC000) != 0xC000)
v_decoded = 0;
}
break;
// CMP - CMP <Rn>,#<imm8>
// 0 0 1 0 1 Rn imm8
case INST_CMP_OPCODE:
{
m_rn = (inst >> 8) & 0x7;
m_imm= (inst >> 0) & 0xFF;
}
break;
// LDM - LDM <Rn>!,<registers> <Rn> not included in <registers>
// 1 1 0 0 1 Rn register_list
// LDM - LDM <Rn>,<registers> <Rn> included in <registers>
// 1 1 0 0 1 Rn register_list
//case INST_LDM_1_OPCODE:
case INST_LDM_OPCODE:
// STM - STM <Rn>!,<registers>
// 1 1 0 0 0 Rn register_list
case INST_STM_OPCODE:
{
m_rn = (inst >> 8) & 0x7;
m_rd = m_rn;
m_reglist = (inst >> 0) & 0xFF;
}
break;
// LDR - LDR <Rt>, [<Rn>{,#<imm5>}]
// 0 1 1 0 1 imm5 Rn Rt
case INST_LDR_OPCODE:
// LDRB - LDRB <Rt>,[<Rn>{,#<imm5>}]
// 0 1 1 1 1 imm5 Rn Rt
case INST_LDRB_OPCODE:
// LDRH - LDRH <Rt>,[<Rn>{,#<imm5>}]
// 1 0 0 0 1 imm5 Rn Rt
case INST_LDRH_OPCODE:
// STR - STR <Rt>, [<Rn>{,#<imm5>}]
// 0 1 1 0 0 imm5 Rn Rt
case INST_STR_OPCODE:
// STRB - STRB <Rt>,[<Rn>,#<imm5>]
// 0 1 1 1 0 imm5 Rn Rt
case INST_STRB_OPCODE:
// STRH - STRH <Rt>,[<Rn>{,#<imm5>}]
// 1 0 0 0 0 imm5 Rn Rt
case INST_STRH_OPCODE:
{
m_imm= (inst >> 6) & 0x1F;
m_rn = (inst >> 3) & 0x7;
m_rt = (inst >> 0) & 0x7;
m_rd = m_rt;
}
break;
// LDR - LDR <Rt>,<label>
// 0 1 0 0 1 Rt imm8
case INST_LDR_2_OPCODE:
{
m_rt = (inst >> 8) & 0x7;
m_rd = m_rt;
m_imm= (inst >> 0) & 0xFF;
}
break;
// LDR - LDR <Rt>,[SP{,#<imm8>}]
// 1 0 0 1 1 Rt imm8
case INST_LDR_1_OPCODE:
// STR - STR <Rt>,[SP,#<imm8>]
// 1 0 0 1 0 Rt imm8
case INST_STR_1_OPCODE:
// ADD - ADD <Rd>,SP,#<imm8>
// 1 0 1 0 1 Rd imm8
case INST_ADD_1_OPCODE:
{
m_rt = (inst >> 8) & 0x7;
m_rn = REG_SP;
m_rd = m_rt;
m_imm= (inst >> 0) & 0xFF;
}
break;
default:
v_decoded = 0;
break;
}
}
// Group 2?
if (!v_decoded)
{
v_decoded = 1;
m_inst_group = INST_IGRP2;