tmp

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -96,7 +96,7 @@ class CSRFileIO(implicit p: Parameters) extends XSBundle {
   val trapTarget = Output(UInt(VAddrBits.W))
   val interrupt = Output(Bool())
   val wfi_event = Output(Bool())
-  val trapTraceInfo = Output(new TrapTraceInfo)
+  val trapTraceInfo = ValidIO(new TrapTraceInfo)
   // from LSQ
   val memExceptionVAddr = Input(UInt(VAddrBits.W))
   val memExceptionGPAddr = Input(UInt(GPAddrBits.W))

src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala

@@ -57,8 +57,8 @@ object CSRBundles {
   }
 
   class PrivState extends Bundle { self =>
-    val PRVM = PrivMode(0)
     val V    = VirtMode(0)
+    val PRVM = PrivMode(0)
 
     def isModeM: Bool = isModeMImpl()
 

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -18,6 +18,7 @@ import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxrm, Vxsat}
 import xiangshan.backend.fu.wrapper.CSRToDecode
 import xiangshan._
 import xiangshan.backend.fu.PerfCounterIO
+import xiangshan.backend.trace._
 
 import scala.collection.immutable.SeqMap
 
@@ -157,6 +158,8 @@ class NewCSR(implicit val p: Parameters) extends Module
       // trigger
       val frontendTrigger = new FrontendTdataDistributeIO()
       val memTrigger = new MemTdataDistributeIO()
+      // trace
+      val trapTraceInfo = ValidIO(new TrapTraceInfo)
       // custom
       val custom = new CSRCustomState
     })
@@ -897,6 +900,13 @@ class NewCSR(implicit val p: Parameters) extends Module
    * debug_end
    */
 
+  // trace
+  val privState1HForTrace = Seq(privState.isModeM, privState.isModeHS, privState.isModeVS)
+  io.status.trapTraceInfo.valid := RegNext(io.fromRob.trap.valid)
+  io.status.trapTraceInfo.bits.priv  := Mux(debugMode, io.status.trapTraceInfo.bits.priv.D, privState.asUInt).asTypeOf(new PrivEnum)
+  io.status.trapTraceInfo.bits.cause := Mux1H(privState1HForTrace, Seq(mcause.rdata, scause.rdata, vscause.rdata))
+  io.status.trapTraceInfo.bits.tval  := Mux1H(privState1HForTrace, Seq(mtval.rdata, stval.rdata, vstval.rdata))
+
   /**
    * perf_begin
    * perf number: 29 (frontend 8, ctrlblock 8, memblock 8, huancun 5)

src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala

@@ -242,7 +242,7 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
   csrOut.debugMode := csrMod.io.status.debugMode
 
   // todo: trace
-  csrOut.trapTraceInfo := DontCare
+  csrOut.trapTraceInfo := csrMod.io.status.trapTraceInfo
 
   csrOut.customCtrl match {
     case custom =>

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -32,7 +32,7 @@ import xiangshan.ExceptionNO._
 import xiangshan.backend.fu.FuType._
 import xiangshan.mem.{EewLog2, GenUSWholeEmul}
 import xiangshan.mem.GenRealFlowNum
-import xiangshan.backend.trace.{IlastsizeEnum, OpRegType, jumpTypeGen}
+import xiangshan.backend.trace._
 
 class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents {
 
@@ -189,6 +189,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     uop.srcLoadDependency := DontCare
     uop.numLsElem       :=  DontCare
     uop.hasException  :=  DontCare
+    uop.traceBlockInPipe := DontCare
   })
   private val fuType       = uops.map(_.fuType)
   private val fuOpType     = uops.map(_.fuOpType)
@@ -403,9 +404,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   /**
    * trace begin
    */
-  val canRobCompressVec = io.in.map(in => in.bits.canRobCompress)
-  val isRVCVec = io.in.map(in => in.bits.preDecodeInfo.isRVC)
-  val jumpTypeVec = io.in.map(in => jumpTypeGen(in.bits.preDecodeInfo.brType, in.bits.ldest.asTypeOf(new OpRegType), in.bits.lsrc(0).asTypeOf((new OpRegType))))
+  val inVec = io.in.map(_.bits)
+  val canRobCompressVec = inVec.map(_.canRobCompress)
+  val isRVCVec = inVec.map(_.preDecodeInfo.isRVC)
   val halfWordNumVec = (0 until RenameWidth).map{
     i => compressMasksVec(i).asBools.zip(isRVCVec).map{
       case (mask, isRVC) => Mux(mask, Mux(isRVC, 1.U, 2.U), 0.U)
@@ -415,28 +416,27 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   for (i <- 0 until RenameWidth) {
     // iretire
     uops(i).traceBlockInPipe.iretire := Mux(canRobCompressVec(i),
-      Mux(needRobFlags(i), halfWordNumVec(i).reduce(_ + _), 0.U), // compress
-      Mux(isRVCVec(i), 1.U, 2.U)                                  // noncompress
+      halfWordNumVec(i).reduce(_ + _),
+      Mux(isRVCVec(i), 1.U, 2.U)
     )
 
     // ilastsize
     val j = i
-    val lastIsRVC = Wire(Bool())
+    val lastIsRVC = WireInit(false.B)
     (j until RenameWidth).map { j =>
-      when(needRobFlags(i) && compressMasksVec(i)(j)) {
+      when(compressMasksVec(i)(j)) {
         lastIsRVC := io.in(j).bits.preDecodeInfo.isRVC
       }
     }
 
     uops(i).traceBlockInPipe.ilastsize := Mux(canRobCompressVec(i),
       Mux(lastIsRVC, IlastsizeEnum.HalfWord, IlastsizeEnum.Word),
       Mux(isRVCVec(i), IlastsizeEnum.HalfWord, IlastsizeEnum.Word)
-    )
+    ).asTypeOf(new IlastsizeEnum)
 
     // itype
-    uops(i).traceBlockInPipe.itype := Mux(canRobCompressVec(i), 0.U, jumpTypeVec(i))
+    uops(i).traceBlockInPipe.itype.jumpTypeGen(inVec(i).preDecodeInfo.brType, inVec(i).ldest.asTypeOf(new OpRegType), inVec(i).lsrc(0).asTypeOf((new OpRegType)))
   }
-
   /**
    * trace end
    */

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -35,6 +35,7 @@ import xiangshan.backend.fu.vector.Bundles.VType
 import xiangshan.backend.rename.SnapshotGenerator
 import yunsuan.VfaluType
 import xiangshan.backend.rob.RobBundles._
+import xiangshan.backend.trace.ItypeEnum
 
 class Rob(params: BackendParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
   override def shouldBeInlined: Boolean = false
@@ -1082,33 +1083,43 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   io.headNotReady := commit_vDeqGroup.head && !commit_wDeqGroup.head
 
   /**
-   * trace io.commits.info.commitentry -> io.commits.traceInterface
-   * todo: pipeline from csr
+   * trace
+   * todo：iaddr should have read from pcmem
    */
-  val trapTraceInfo = io.commits.traceInterface.toEncoder.trapTraceInfo
+  val trapTraceInfoFromCsr = io.csr.trapTraceInfo
   val traceBlocks = io.commits.traceInterface.toEncoder.blocks
   val traceBlockInPipe = io.commits.traceInterface.toEncoder.blocks.map(_.traceBlockInPipe)
-  trapTraceInfo := io.csr.trapTraceInfo
+
+  io.commits.traceInterface.toEncoder.trapTraceInfo := trapTraceInfoFromCsr.bits
 
   for (i <- 0 until CommitWidth) {
     traceBlocks(i).iaddr := io.commits.info(i).debug_pc.get  //todo： should have read from pcmem
-    traceBlockInPipe(i).itype :=Mux(
+    traceBlockInPipe(i).itype := Mux(
       CommitType.isBranch(io.commits.info(i).commitType),
-      Mux(io.commits.info(i).taken, traceBlockInPipe(i).itype.Taken, traceBlockInPipe(i).itype.NonTaken),
-      Mux(io.csr.isXRet, traceBlockInPipe(i).itype.ExpIntReturn, io.commits.info(i).traceBlockInPipe.itype)
-    )
-    traceBlockInPipe(i).iretire := io.commits.info(i).traceBlockInPipe.iretire
-    traceBlockInPipe(i).ilastsize := io.commits.info(i).traceBlockInPipe.ilastsize.asUInt
+      Mux(io.commits.info(i).taken, ItypeEnum.Taken, ItypeEnum.NonTaken),
+      Mux(io.csr.isXRet, ItypeEnum.ExpIntReturn, io.commits.info(i).traceBlockInPipe.itype.asUInt)
+    ).asTypeOf( traceBlockInPipe(i).itype)
+    traceBlockInPipe(i).iretire := Mux(io.commits.isCommit && io.commits.commitValid(i), io.commits.info(i).traceBlockInPipe.iretire, 0.U)
+    traceBlockInPipe(i).ilastsize := io.commits.info(i).traceBlockInPipe.ilastsize
   }
 
-  when(io.exception.valid){ //todo: 不止异常 还有flush pipe
-    traceBlocks(0).traceBlockInPipe.itype := Mux(io.exception.bits.isInterrupt, 
-      traceBlocks(0).traceBlockInPipe.itype.Interrupt, 
-      traceBlocks(0).traceBlockInPipe.itype.Exception
-    ) //todo:发生异常和中断时的处理
-    traceBlocks(0).traceBlockInPipe.iretire := Mux(io.flushOut.bits.level.asBool, 0.U, traceBlocks(0).traceBlockInPipe.iretire)
-  }
 
+  val t_idle :: t_waiting :: Nil = Enum(2)
+  val traceState = RegInit(t_idle)
+  when(traceState === t_idle){
+    when(io.exception.valid){
+      traceState := t_waiting
+    }
+  }.elsewhen(traceState === t_waiting){
+    when(trapTraceInfoFromCsr.valid){
+      traceState := t_idle
+
+      traceBlocks(0).traceBlockInPipe.itype := Mux(io.exception.bits.isInterrupt,
+        ItypeEnum.Interrupt,
+        ItypeEnum.Exception
+      ).asTypeOf(new ItypeEnum)
+    }
+  }
 
   /**
    * debug info

src/main/scala/xiangshan/backend/rob/RobBundles.scala

@@ -231,7 +231,7 @@ class RobCSRIO(implicit p: Parameters) extends XSBundle {
   val trapTarget = Input(UInt(VAddrBits.W))
   val isXRet     = Input(Bool())
   val wfiEvent   = Input(Bool())
-  val trapTraceInfo = Input(new TrapTraceInfo)
+  val trapTraceInfo = Flipped(ValidIO(new TrapTraceInfo))
 
   val fflags     = Output(Valid(UInt(5.W)))
   val vxsat      = Output(Valid(Bool()))

src/main/scala/xiangshan/backend/trace/Interface.scala

@@ -8,7 +8,7 @@ import xiangshan.frontend.{BrType, PreDecodeInfo}
 
 trait TraceConfig extends HasXSParameter {
   implicit val p: Parameters
-  def causeWidth = 6 //64
+  def causeWidth = XLEN //64
   def tvalWidth = XLEN
   def privWidth = 3
 
@@ -33,7 +33,7 @@ class Interface(implicit val p: Parameters) extends Bundle with TraceConfig {
 class TrapTraceInfo(implicit val p: Parameters) extends Bundle with TraceConfig {
   val cause = UInt(causeWidth.W)
   val tval  = UInt(tvalWidth.W)
-  val priv  = new PrivEnum(privWidth)
+  val priv  = new PrivEnum
 }
 
 class TraceBlock(implicit val p: Parameters) extends Bundle with TraceConfig {
@@ -42,13 +42,13 @@ class TraceBlock(implicit val p: Parameters) extends Bundle with TraceConfig {
 }
 
 class TraceBlockInPipe(implicit val p: Parameters) extends Bundle with TraceConfig {
-  val itype     = new ItypeEnum(itypeWidth)
+  val itype     = new ItypeEnum
   val iretire   = UInt(iretireWidth.W)
   val ilastsize = new IlastsizeEnum
 }
 
-class ItypeEnum(width: Int) extends Bundle {
-  val value                = UInt(width.W)
+class ItypeEnum extends Bundle {
+  val value                = UInt(4.W)
   def None                 = 0.U
   def Exception            = 1.U    //rob
   def Interrupt            = 2.U    //rob
@@ -68,11 +68,48 @@ class ItypeEnum(width: Int) extends Bundle {
   def clear(): Unit = {
     this.value := None
   }
+
+  def jumpTypeGen(brType: UInt, rd: OpRegType, rs: OpRegType): ItypeEnum = {
+
+    val isEqualRdRs = rd === rs
+    val isJal       = brType === BrType.jal
+    val isJalr      = brType === BrType.jalr
+
+    // push to RAS when rd is link, pop from RAS when rs is link
+    def isUninferableCall      = isJalr && rd.isLink && (!rs.isLink || rs.isLink && isEqualRdRs)  //8   push
+    def isInferableCall        = isJal && rd.isLink                                               //9   push
+    def isUninferableTailCall  = isJalr && rd.isX0 && !rs.isLink                                  //10  no op
+    def isInferableTailCall    = isJal && rd.isX0                                                 //11  no op
+    def isCoRoutineSwap        = (isJalr && rd.isLink && rs.isLink && !isEqualRdRs)               //12  pop then push
+    def isFunctionReturn       = (isJalr && !rd.isLink && rs.isLink)                              //13  pop
+    def isOtherUninferableJump = (isJalr && !rd.isLink && !rd.isX0 && !rs.isLink)                 //14  no op
+    def isOtherInferableJump   = isJal && !rd.isLink && !rd.isX0                                  //15  no op
+
+    val jumpType = Mux1H(
+      Seq(
+        isUninferableCall,
+        isInferableCall,
+        isUninferableTailCall,
+        isInferableTailCall,
+        isCoRoutineSwap,
+        isFunctionReturn,
+        isOtherUninferableJump,
+        isOtherInferableJump,
+      ),
+      (8 to 15).map(i => i.U)
+    )
+    Mux(isJal || isJalr, jumpType, 0.U).asTypeOf(new ItypeEnum)
+  }
+
   // supportSijump
   def isUninferable = Seq(UninferableCall, UninferableTailCall, CoRoutineSwap,
     UninferableTailCall, OtherUninferableJump).map(_ === this.value).reduce(_ || _)
 }
 
+object ItypeEnum extends ItypeEnum{
+  def apply = new ItypeEnum
+}
+
 class IlastsizeEnum extends Bundle {
   val value = UInt(1.W)
   def HalfWord = 0.U
@@ -83,8 +120,8 @@ object IlastsizeEnum extends IlastsizeEnum {
   def apply()   = new IlastsizeEnum
 }
 
-class PrivEnum(width: Int) extends Bundle {
-  val value = UInt(width.W)
+class PrivEnum extends Bundle {
+  val value = UInt(3.W)
   def HU = 0.U
   def HS = 1.U
   def M  = 3.U
@@ -102,21 +139,38 @@ class OpRegType extends Bundle {
   def isLink = Seq(isX1, isX5).map(_ === this.value).reduce(_ || _)
 }
 
-def jumpTypeGen(brType: UInt, rd: OpRegType, rs: OpRegType): UInt ={
-
+class JumpTypeGen extends Module{
+  val in = Input(new Bundle {
+    val brType = UInt(2.W)
+    val rd = new OpRegType
+    val rs = new OpRegType
+  })
+  val out = Output(new Bundle {
+    val jumpType = UInt(4.W)
+  })
+
+  val (brType, rd, rs) = (in.brType, in.rd, in.rs)
+
   val isEqualRdRs = rd === rs
-  val isJal       = brType === BrType.jal
-  val isJalr      = brType === BrType.jalr
+  val isJal = brType === BrType.jal
+  val isJalr = brType === BrType.jalr
 
   // push to RAS when rd is link, pop from RAS when rs is link
-  def isUninferableCall      = isJalr && rd.isLink && (!rs.isLink || rs.isLink && isEqualRdRs)  //8   push
-  def isInferableCall        = isJal && rd.isLink                                               //9   push
-  def isUninferableTailCall  = isJalr && rd.isX0 && !rs.isLink                                  //10  no op
-  def isInferableTailCall    = isJal && rd.isX0                                                 //11  no op
-  def isCoRoutineSwap        = (isJalr && rd.isLink && rs.isLink && !isEqualRdRs)               //12  pop then push
-  def isFunctionReturn       = (isJalr && !rd.isLink && rs.isLink)                              //13  pop
-  def isOtherUninferableJump = (isJalr && !rd.isLink && !rd.isX0 && !rs.isLink)                 //14  no op
-  def isOtherInferableJump   = isJal && !rd.isLink && !rd.isX0                                  //15  no op
+  def isUninferableCall = isJalr && rd.isLink && (!rs.isLink || rs.isLink && isEqualRdRs) //8   push
+
+  def isInferableCall = isJal && rd.isLink //9   push
+
+  def isUninferableTailCall = isJalr && rd.isX0 && !rs.isLink //10  no op
+
+  def isInferableTailCall = isJal && rd.isX0 //11  no op
+
+  def isCoRoutineSwap = (isJalr && rd.isLink && rs.isLink && !isEqualRdRs) //12  pop then push
+
+  def isFunctionReturn = (isJalr && !rd.isLink && rs.isLink) //13  pop
+
+  def isOtherUninferableJump = (isJalr && !rd.isLink && !rd.isX0 && !rs.isLink) //14  no op
+
+  def isOtherInferableJump = isJal && !rd.isLink && !rd.isX0 //15  no op
 
   val jumpType = Mux1H(
     Seq(
@@ -131,5 +185,15 @@ def jumpTypeGen(brType: UInt, rd: OpRegType, rs: OpRegType): UInt ={
     ),
     (8 to 15).map(i => i.U)
   )
-  Mux(isJal || isJalr, jumpType, 0.U)
+   out.jumpType := Mux(isJal || isJalr, jumpType, 0.U)
 }
+
+object JumpTypeGen {
+  def apply(brType: UInt, rd: OpRegType, rs: OpRegType): UInt = {
+    val jumpTypeGen = Module(new JumpTypeGen)
+    jumpTypeGen.brType := brType
+    jumpTypeGen.rd := rd
+    jumpTypeGen.rs := rs
+    jumpTypeGen.out.jumpType
+  }
+}