Add stm32u0 series #145644
Annotations
1 error, 1 warning, and 10 notices
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Run Compliance Tests
Process completed with exit code 1.
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check-warns:
ClangFormat.txt#L1
See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
You may want to run clang-format on this change:
-
File:drivers/clock_control/clock_stm32g0_u0.c
Line:9
You may want to run clang-format on this change:
-__unused
-static uint32_t get_pll_source(void)
+__unused static uint32_t get_pll_source(void)
File:drivers/clock_control/clock_stm32g0_u0.c
Line:27
You may want to run clang-format on this change:
-__unused
-uint32_t get_pllsrc_frequency(void)
+__unused uint32_t get_pllsrc_frequency(void)
File:drivers/clock_control/clock_stm32g0_u0.c
Line:44
You may want to run clang-format on this change:
-__unused
-void config_pll_sysclock(void)
+__unused void config_pll_sysclock(void)
{
- LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
- pllm(STM32_PLL_M_DIVISOR),
- STM32_PLL_N_MULTIPLIER,
- pllr(STM32_PLL_R_DIVISOR));
+ LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(), pllm(STM32_PLL_M_DIVISOR),
+ STM32_PLL_N_MULTIPLIER, pllr(STM32_PLL_R_DIVISOR));
File:drivers/clock_control/clock_stm32g0_u0.c
Line:65
You may want to run clang-format on this change:
File:drivers/clock_control/clock_stm32g0_u0.c
Line:90
You may want to run clang-format on this change:
- LOG_DBG("Status: 0x%08lx",
- (unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
- FLASH_STM32_SR_ERRORS);
+ LOG_DBG("Status: 0x%08lx", (unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
+ FLASH_STM32_SR_ERRORS);
File:drivers/flash/flash_stm32.c
Line:97
You may want to run clang-format on this change:
-#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
File:include/zephyr/drivers/clock_control/stm32_clock_control.h
Line:152
You may want to run clang-format on this change:
-#define STM32_CLOCK_BUS_IOP 0x4C
-#define STM32_CLOCK_BUS_AHB1 0x48
-#define STM32_CLOCK_BUS_APB1 0x58
-#define STM32_CLOCK_BUS_APB1_2 0x60
+#define STM32_CLOCK_BUS_IOP 0x4C
+#define STM32_CLOCK_BUS_AHB1 0x48
+#define STM32_CLOCK_BUS_APB1 0x58
+#define STM32_CLOCK_BUS_APB1_2 0x60
-#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
-#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
+#define STM32_PERIPH_BUS_MIN STM32_CLOCK_
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Run Compliance Tests:
drivers/clock_control/clock_stm32g0_u0.c#L9
drivers/clock_control/clock_stm32g0_u0.c:9
-
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Run Compliance Tests:
drivers/clock_control/clock_stm32g0_u0.c#L27
drivers/clock_control/clock_stm32g0_u0.c:27
-__unused
-static uint32_t get_pll_source(void)
+__unused static uint32_t get_pll_source(void)
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Run Compliance Tests:
drivers/clock_control/clock_stm32g0_u0.c#L44
drivers/clock_control/clock_stm32g0_u0.c:44
-__unused
-uint32_t get_pllsrc_frequency(void)
+__unused uint32_t get_pllsrc_frequency(void)
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Run Compliance Tests:
drivers/clock_control/clock_stm32g0_u0.c#L65
drivers/clock_control/clock_stm32g0_u0.c:65
-__unused
-void config_pll_sysclock(void)
+__unused void config_pll_sysclock(void)
{
- LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
- pllm(STM32_PLL_M_DIVISOR),
- STM32_PLL_N_MULTIPLIER,
- pllr(STM32_PLL_R_DIVISOR));
+ LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(), pllm(STM32_PLL_M_DIVISOR),
+ STM32_PLL_N_MULTIPLIER, pllr(STM32_PLL_R_DIVISOR));
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Run Compliance Tests:
drivers/clock_control/clock_stm32g0_u0.c#L90
drivers/clock_control/clock_stm32g0_u0.c:90
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Run Compliance Tests:
drivers/flash/flash_stm32.c#L97
drivers/flash/flash_stm32.c:97
- LOG_DBG("Status: 0x%08lx",
- (unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
- FLASH_STM32_SR_ERRORS);
+ LOG_DBG("Status: 0x%08lx", (unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &
+ FLASH_STM32_SR_ERRORS);
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Run Compliance Tests:
include/zephyr/drivers/clock_control/stm32_clock_control.h#L152
include/zephyr/drivers/clock_control/stm32_clock_control.h:152
-#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
- DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
+ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
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Run Compliance Tests:
include/zephyr/dt-bindings/clock/stm32u0_clock.h#L19
include/zephyr/dt-bindings/clock/stm32u0_clock.h:19
-#define STM32_CLOCK_BUS_IOP 0x4C
-#define STM32_CLOCK_BUS_AHB1 0x48
-#define STM32_CLOCK_BUS_APB1 0x58
-#define STM32_CLOCK_BUS_APB1_2 0x60
+#define STM32_CLOCK_BUS_IOP 0x4C
+#define STM32_CLOCK_BUS_AHB1 0x48
+#define STM32_CLOCK_BUS_APB1 0x58
+#define STM32_CLOCK_BUS_APB1_2 0x60
-#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
-#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
+#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
+#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
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Run Compliance Tests:
include/zephyr/dt-bindings/clock/stm32u0_clock.h#L38
include/zephyr/dt-bindings/clock/stm32u0_clock.h:38
-#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
-#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
-#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
-#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
+#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
+#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
+#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
+#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
/** Peripheral bus clock */
-#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
+#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
/** PLL clock outputs */
-#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
-#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
-#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
+#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
+#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
+#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
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Run Compliance Tests:
include/zephyr/dt-bindings/clock/stm32u0_clock.h#L90
include/zephyr/dt-bindings/clock/stm32u0_clock.h:90
-#define STM32_CLOCK(val, mask, shift, reg) \
- ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
- (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
- (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
+#define STM32_CLOCK(val, mask, shift, reg) \
+ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
+ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
+ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
/** @brief RCC_CCIPR register offset */
-#define CCIPR_REG 0x88
+#define CCIPR_REG 0x88
/** @brief RCC_BDCR register offset */
-#define BDCR_REG 0x90
+#define BDCR_REG 0x90
/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
-#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
-#define LPUART3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
-#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
-#define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
-#define TIM1_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
-#define TIM15_SEL(val) STM32_CLOCK(val, 1, 25, CCIPR_REG)
-#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
+#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
+#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
+#define LPUART3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
+#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
+#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
+#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
+#define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG)
+#define TIM1_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
+#define TIM15_SEL(val) STM32_CLOCK(val, 1, 25, CCIPR_REG)
+#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
+#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG)
/** BDCR devices */
-#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR_REG)
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