TaiLung RV32I

Designinig a Pipelined in-order 5 stage RISC-V core RV32I-MF

Architecture

Documents

Intro to the project

HAS (high-level architecture specs)

MAS (microarchitecture specs)

TFM (tools, flows, & methodologies

Validation plan

Getting started

prerequisities

1. a working linux termimnal (WSL, ubuntu, Etc...).
2. python3 or higher installed follow this link
3. RISC-V GCC toolchain installed follow this link
4. Intel ModelSim simulator installed follow this link

clone repo

git clone https://github.com/ChrisShakkour/RV32I-MAF-project.git 

cd and source

cd RV32I-MAF-project
source source_me.sh

Compile RTL design

compile_hdl -top CoreTop_TB

how to use compile_hdl

compile C code

compile_gcc -src <some c source file> -elf -txt -mem

how to use compile_gcc

System-level simulation

simulate -test <test name>

how to use simulate

Example

git clone https://github.com/ChrisShakkour/RV32I-MAF-project.git
cd RV32I-MAF-project
source source_me.sh
compile_hdl -top CoreTop_TB
compile_gcc -src verif/tests/TowerOfHanoi/TowerOfHanoi.c -elf -txt -mem
simulate -test TowerOfHanoi

References

What's next?