Library for VLSI CAD Design Useful parsers and solvers' api are implemented.

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Microshift Compression: An Efficient Image Compression Algorithm for Hardware

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Gatery, a library for circuit design.

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Spiking Neural Network Accelerator

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

32-bit RISC-V microcontroller

Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)

This is part of EC383 - Mini Project in VLSI Design.

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

The Repository contains the code of various Digital Circuits

We are designing a CP-PLL. The following link provides resources about PLL design.

UART - RTL Design and Verification