Merge pull request #58 from PedroAntunes178/master

SoC: remove PLIC and CLINT submodules, fix axi_ram, passes in Kintex FPGA.
IObundle · Oct 28, 2023 · 6231f85 · 6231f85
2 parents 28e13a4 + b907d70
commit 6231f85
Show file tree

Hide file tree

Showing 9 changed files with 362 additions and 477 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -1,15 +1,9 @@
 [submodule "submodules/VEXRISCV"]
 	path = submodules/VEXRISCV
 	url = [email protected]:IObundle/iob-vexriscv.git
-[submodule "submodules/CLINT"]
-	path = submodules/CLINT
-	url = [email protected]:IObundle/iob-clint.git
 [submodule "submodules/UART16550"]
 	path = submodules/UART16550
 	url = [email protected]:IObundle/iob-uart16550.git
-[submodule "submodules/PLIC"]
-	path = submodules/PLIC
-	url = [email protected]:IObundle/iob-plic.git
 [submodule "submodules/OS"]
 	path = submodules/OS
 	url = [email protected]:IObundle/iob-linux.git

diff --git a/Makefile b/Makefile
@@ -8,8 +8,9 @@ DISABLE_LINT:=1
 LIB_DIR:=submodules/IOBSOC/submodules/LIB
 include $(LIB_DIR)/setup.mk
 
-INIT_MEM ?= 1
-RUN_LINUX ?= 1
+INIT_MEM ?= 0
+RUN_LINUX ?= 0
+USE_EXTMEM := 1
 
 ifeq ($(INIT_MEM),1)
 SETUP_ARGS += INIT_MEM