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Nanomips mtk/nanomips merge #39

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Nanomips mtk/nanomips merge #39

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Merging of the mtk/nanomips branch into the nanomips branch. Branch merging went without conflicts. No errors occurred while building the llvm-project.

After running the ninja check-all, five new tests are now failing:

  • LLVM :: CodeGen/Mips/nanomips/m_o_zc_constraints.ll
    • ll instructions now have invalid operand (report by integrated-as), should be changed to correct ones
    • addiu[48] is expected, but it should be changed to addiu
    • first occurrence of Subtarget->hasNanoMips() (inside if statement) needs to be removed in order to reach correct piece of code that handles Constraint_ZC for NanoMIPS target ( function: MipsSEDAGToDAGISel:: SelectInlineAsmMemoryOperand, line: 1572)
  • LLVM :: CodeGen/Mips/nanomips/outliner_test.ll
    • at the point of jumping to an outlined function, the generated instruction is bc instead of the expected balc
  • LLVM :: CodeGen/Mips/nanomips/outliner_test_regsave.mir
    • SAVE16_NM is generated instead of SAVE_NM
  • LLVM :: CodeGen/Mips/nanomips/outliner_test_thunk.ll
    • at the point of jumping to an outlined function, the generated instruction is bc instead of the expected balc
  • LLVM :: MC/Mips/nanomips/exp-relocs.s
    • Assertion isImm() && "This is not an immediate" failed (file: llvm-project/llvm/include/llvm/MC/MCInst.h, line: 81)
    • expected string not found in input: # CHECK: R_NANOMIPS_NOTRAMP *ABS*

Colin McEwan and others added 30 commits August 10, 2023 02:12
Add csmith-generated tests
0853501 
Change-Id: Icd1b11638dcca6ebe65db5cf44698e4038d34891
Revert "Add csmith-generated tests"
b99c5d1 
This reverts commit 0853501.
Merge remote-tracking branch 'origin/nanomips' into mtk/nanomips
b114c87
Merge remote-tracking branch 'origin/nanomips' into mtk/nanomips
a02e638
Make sharing of debug info across compilation units optional
c497461 
Change-Id: I4d1b41912d770abf4a6cc85e163f078be1cb91f1
@farazs-github
Optimize multiple accesses to the same base with larger offsets
e12de29 
... by reusing existing offset in CodeGenPrepare.

Added NanoMipsCodeGenPrepare pass witch munges constant geps into
a form that later can be optimized by generic CodeGenPrepare.

Change-Id: Ib54643a0eca9c8a2aa7cc7ce38c7b296e4ca0e6e
@farazs-github
Combine reg + symbol into addiu[48]
6cc1661 
This change makes code references not fully pc-relative.

Change-Id: I829687d892b86c46ba84a24c4e93de1a21574c4c
@farazs-github
Fix atomic builtins code-gen
f5ff4ad 
nanoMIPS ISA does not natively support ORI/ANDI with 16-bit immediate
operands. As a result, ORIs are generated incorrectly in atomic
builtin expansions with the immediate value being clipped above
bit 11. ANDIs may be correct if using a 3-bit register encoding, else
they end up relying on GNU assemblers instruction aliases using EXT.

This replaces the potentially problematic instructions with
natively supported nanoMIPS instructions. Some expansions are
sub-optimal on account of preferring 32-bit instructions even
where 16-bit encoding is possible.

Change-Id: I0f40a61e4f22a58bb91b3f11a6bd01a29452614e
@farazs-github
Add NanoMips ELF machine type and header flags
95fe0b4 
Use EM_NANOMIPS for generated nanomips-elf objects

Change-Id: I4e4d759c006c3f08341fdd428de2c99d0ca200b7
@farazs-github
Register assembler, disassembler and object emitter for NanoMips
82a5c45 
Change-Id: Idb31afcc5aab0ad803c54ca126d4b95e69c380a9
@farazs-github
Emit instructions in NanoMips byte order
2929392 
Use 64-bit doublewords to handle 48-bit instructions.

Change-Id: I6f2c1cdd51d3de156d6013fc9b583392d7606ab6
@farazs-github
Add a nanoMIPS parser variant to allow brackets in mnemonics
0c6f3d9 
Change-Id: Ib61ddb42057eaa631b5c4aa219ca76b291835702
@farazs-github
Add NanoMips relocations
772b793 
Change-Id: I8a016e06544a07b80902652622a7ff41554ce306
@farazs-github
Show relocation encoding comments in nanoMIPS instruction byte order
51db031 
Change-Id: I4182172fc84d9cf854cab15ebc3983ab34f804a6
@farazs-github
Add front-end assembler directives and set ELF header flags
85cc408 
Change-Id: I1404c1a21f6df683d5f1aaac36349175e89a2e23
@farazs-github
Refactor GPR32NM to GPR32NM
9db2fd0 
Change-Id: Ib2bcaaee8d04aa089fd438df7c039a12ff0085f5
@farazs-github
Refactor ADDiu_NM to ADDIU_NM
93a90e3 
Change-Id: I11b042ff5d97834e69d3250548c2a1d2d1d03f6e
@farazs-github
Refactor LEA_ADDiu_NM to LEA_ADDIU_NM
ede1c33 
Change-Id: I53f986f2c8e0e5f7184c4e362e3c27934f99d7ed
@farazs-github
Refactor Li_NM to LI48_NM
d5829fc 
Change-Id: Id68922845b03f20e040ad393abaa719ffc57f5a6
@farazs-github
Add NanoMips register names and new register operand types
ccb0e0c 
Change-Id: Ib2483ab1ad593493c88a5e7b51f157ea1ca23a88
@farazs-github
Add encodings for NanoMips instruction pools
418a397 
Change-Id: I7d3653a2bd47e0d0bbfc93ccb1e74beea9e9e15e
@farazs-github
Fix decoding logic for 16, 32 & 48-bit nanoMIPS instructions
2196ea0 
Change-Id: I8c0c4213a7afabec7308766c7050e3fba3d0b02d
@farazs-github
Parse and encode arithmetic/logic instructions
42de2b1 
Change-Id: Ia359143068c9edbb0dfe748c3c704c0db048bd72
@farazs-github
Parse and encode address calculation instructions, PC-relative loads/…
9354878 
…stores + refactor LA_NM to ADDIUPC48_NM

Change-Id: I533ac72eb3656c884b4107868db66fa2e1c3cfbf
@farazs-github
Parse and encode load/store instructions
41fa74d 
Change-Id: Ifde8c84908318ccd4555b3001374f3972de5d0ae
@farazs-github
Parse and encode control transfer instructions
396ba11 
Change-Id: I073a947236a401e0f1f43d634b4c069fa9a66547
@farazs-github
Parse and encode MOVE variants
17ff15a 
Change-Id: I1f305d006273c90cb93ef8f65b626484c3859fb6
@farazs-github
Parse and encode SAVE/RESTORE variants
033e2b0 
Change-Id: Ib4aae7e3c6b44d9ff326c5c282951802f8f3548f
@farazs-github
Parse and encode supervisor and control level instructions
3dbccaf 
Change-Id: I400f6f9f20d631a59730a1829b1a97223e3288fb
@farazs-github
Don't disable integrated assembler for NanoMips
699f91e 
Providing an interface for useIntegrateAs over-rides
the command-line option. Removing it allows us to control
the use of integrated assembler from the command-line.

Change-Id: I3326038c76e742dbbb906c39bd6f087db8cbbd96
farazs-github and others added 24 commits December 13, 2023 19:11
@farazs-github
Add LA pseudo opcode to expand to LI/LAPC
8506e23 
Change-Id: I2dbd5e00ce450cf966f60d836a9b42ff954925d5
@farazs-github
Add SUBU pseudo to subtract immediate operand
9181dbf 
Change-Id: If77b00b39437aeb736603f0de240613aec52594d
@farazs-github
Add ADDIU pseudo operator
73cd878 
Change-Id: Ifa98c5c333b9f332a9c8c5aed824c3fefdeb2036
@farazs-github
Modify assembly parser to accept macro name after .endm
21da051 
GNU assembler supports this syntax

Change-Id: Iec7fe84c7f1c50886e4edaa69f9f79489a998d72
@farazs-github
Add MnemonicAliases for compact branches
396dfc3 
Change-Id: I47302764c3e4005f9e7609fdf49c85f039978ecc
@farazs-github
Add NanoMips Subset as a subtarget feature
32155d3 
Change-Id: If5dc329ea6fae1a80cc58223164e598a61f4c35c
@farazs-github
Parse and encode BEQZC/BNEZC alias forms
9bf30f7 
Change-Id: Ib239b18b5fe2d2e91e82dd19e31d4d4a27cf0d97
@farazs-github
Roll-back change to register pressure limit for nanoMIPS registers
9a2da4a 
The erstwhile default which assumes that the general purpose register
set is always under high pressure leads to better allocation on
average than the general MIPS model which allows free allocation of
up to 28 registers.  Revert to earlier behaviour for now, to be looked
in to along with scheduling changes.

Change-Id: I2e8b04edf49552a591f4f65cd33aef652a44e88e
@farazs-github
Test-suite update - follow-up patch
a50480d 
Change-Id: I8fee60e432e8619a79a95c1ca0142de36f242184
@farazs-github
Enable IntegratedAssembler by default for NanoMips
00a5e38 
Change-Id: I0b36e83828d5f8641ddf70fb7b1b56c3d77235ad
@farazs-github
Emit section-relative relocations for .rodata
f1cd862 
Change-Id: Iea67daf6e020de023b8b6c76e60af75b2d2e49dd
@farazs-github
Set correct AssemblerDialect for ParseInstruction
c4172d3 
The assembler dialect in the parser class is only set up when parsing
assembly files.  For inline assembly, it must be obtained from
AsmInfo in order to correctly reflect the ISA mode.

Change-Id: Iea23bcbc365fe127d1f2a0ba113db6a46012286e
@farazs-github
Fix PseudoLI expansion for symbol address
d88a275 
Change-Id: Ic38cc32a089b7682a9cd77169e3db28ecb56667d
@farazs-github
Assemble calls to 32-bits by default and use BALC[16] for 16-bit calls
826e04b 
Inheritance structure of ParserMatchClass determines the order of
instructions in MatchTable.  Inherit 25-bit call operand from
10-bit call operand in order to prioritize it.

This is required for balc-stubs optimization in the linker.

Change-Id: I3c96d1f61862e76936e5b444bbe6280d031ed6b1
@farazs-github
Add R_NANOMIPS_NOTRAMP relocation and handling for R_NANOMIPS_NONE
486224f 
* R_NANOMIPS_TRAMP needed to inhibit stub optimization
* R_NANOMIPS_NONE backend handling was missing. Added for sake of completeness.

Change-Id: I3382994a7a67edc6fbe13a5ac1622934ad05da16
@farazs-github
Add support for explicit place-holder relocations
fba25ec 
Change-Id: Ie09b2dc1f7041c33ba67525a3e6e59144eed5af0
@farazs-github
Emit PC-relative relocation for immediate branch operands
adce66b 
Typical branch target is represented as a symbol and the assembler
emits a relocation that the linker resolves to the final branch
address. For immediate operands as well, we can treat the operand as
a target address and emit a relocation that the linker can resolve
to reach that address. This patch brings integrated assembler's
handling of immediate operands in line with GNU assembler.

Change-Id: Ic72fe65cb5f5617b844bd0f7ef9803be0d17d28e
@farazs-github
Add signed and shift relocations for jump table optimization
de780a5 
* Add support for converting .shword and .sbyte data directives
to R_NANOMIPS_SIGNED_[8|16] relocations.
* Maps expressions with 1-bit right-shift to R_NANOMIPS_ASHIFTR_1

Change-Id: I2294313664f8eb1cfd2052f39c86e5328b0648d5
@farazs-github
Parse and accept JUMPTABLE_LOAD relocation and jumptable directive
af1bcf0 
* Parse and ignore .jumptable directive
* Parse and ignore R_NANOMIPS_JUMPTABLE_LOAD relocation

This is to facilitate the compiler to enable jump-table compression
regardless of whether it uses integrated or external assembler. It does
not have any impact on object encoding generated by integrated assembler,
but allows the same generated assembly to be handled by either assemblers.

Change-Id: I8f9ed12c7acf5cef11fada62f230ce92cd363750
@farazs-github
Fix register mappings for MFTR/MTTR aliases
13fb389 
Native MTTR/MFTR instructions should only accept COP registers, that
is simple numbered registers as the second operand.  Translate the
incoming registers from the aliases to the correct format.

Change-Id: I778f374feff3ea9022905314c0c2e262b1909f3c
@farazs-github
Make assembly generation responsive to -mno-pcrel & -mno-relax options
486662f 
* Disable linker relaxation by default to match GNU assembler
* Disable PC-relative addressing by default to match GNU assembler
* Don't emit directives to enable PC-relative addressing and linker
relaxations unconditionally in assembly file. Instead check subtarget
features to decide when these must be enabled.
* Test-suite updates to match new defaults

Change-Id: I54f32c77edd7f8ef0352bc6e87ec86ca7c4cec02
@farazs-github
Fix LTO backend for integrated assembler
fec8707 
* Use cc1as as the external assembler when compiling LTO with -fintegrated-as

* When using nanomips-elf-as as external assembler for LTO, pass option
-mlegacyregs to work around different MTTR/MFTR operand constraints.

Change-Id: Ic2540162637dfa76cfe243ac3ab127e259f0e9a9
Add MediaTek copyright notices
1dbc1a3 
Change-Id: Iec6ed1c300c3ce19299d7f8a1005f4df060573d8
Merge branch 'mtk/nanomips' into nanomips-mtk/nanomips-merge
69ef6e7
@djtodoro djtodoro marked this pull request as ready for review February 13, 2024 09:10
@djtodoro
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@farazs-github @cme Ping :)

farazs-github
farazs-github approved these changes Mar 22, 2024
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LGTM. Have you checked llvm-test-suite?

@djtodoro
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djtodoro commented Jun 4, 2024

@nikolaperic did we check the llvm-test-suite? I think yes. If yes, lets merge it.

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@farazs-github farazs-github farazs-github approved these changes

@cme cme Awaiting requested review from cme

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@nikolaperic @djtodoro @farazs-github