Nanomips mtk/nanomips merge

clang/lib/Driver/Driver.cpp

@@ -88,6 +88,7 @@
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/Support/raw_ostream.h"
+#include "mtk/tool_copyright.h"
 #include <map>
 #include <memory>
 #include <utility>
@@ -1779,6 +1780,7 @@ bool Driver::HandleImmediateArgs(const Compilation &C) {
   if (C.getArgs().hasArg(options::OPT__version)) {
     // Follow gcc behavior and use stdout for --version and stderr for -v.
     PrintVersion(C, llvm::outs());
+    llvm::outs() << TOOL_COPYRIGHT << "\n";
     return false;
   }
 
@@ -4325,7 +4327,8 @@ class ToolSelector final {
         return nullptr;
     }
 
-    if (!T->hasIntegratedAssembler())
+    if (!T->hasIntegratedAssembler() ||
+	(TC.getTriple().isNanoMips() && TC.useIntegratedAs()))
       return nullptr;
 
     Inputs = CJ->getInputs();
@@ -4348,7 +4351,8 @@ class ToolSelector final {
     if (!T)
       return nullptr;
 
-    if (!T->hasIntegratedAssembler())
+    if (!T->hasIntegratedAssembler() ||
+	(TC.getTriple().isNanoMips() && TC.useIntegratedAs()))
       return nullptr;
 
     Inputs = BJ->getInputs();

clang/lib/Driver/ToolChains/Arch/Mips.cpp

@@ -423,6 +423,10 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
       Features.push_back("+relax");
     else
       Features.push_back("-relax");
+    if (Args.hasFlag(options::OPT_mpcrel, options::OPT_mno_pcrel, true))
+      Features.push_back("+pcrel");
+    else
+      Features.push_back("-pcrel");
   }
 
 }

clang/lib/Driver/ToolChains/Gnu.cpp

@@ -2805,6 +2805,7 @@ bool Generic_GCC::IsIntegratedAssemblerDefault() const {
   case llvm::Triple::mips64el:
   case llvm::Triple::msp430:
   case llvm::Triple::m68k:
+  case llvm::Triple::nanomips:
     return true;
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:

clang/lib/Driver/ToolChains/NanoMips.cpp

@@ -139,18 +139,37 @@ void NanoMipsLinker::ConstructJob(Compilation &C, const JobAction &JA,
                   D.getLTOMode() == LTOK_Thin);
 
     // No object emitter on NanoMips yet, use external assembler for LTO.
-    CmdArgs.push_back(Args.MakeArgString("--plugin-opt=-lto-external-asm="
-                                         + (getToolChain()
-                                            .GetProgramPath("as"))));
     StringRef CPUName;
     StringRef ABIName;
     mips::getMipsCPUAndABI(Args, getToolChain().getTriple(), CPUName, ABIName);
 
-    CmdArgs.push_back("-plugin-opt=-lto-external-asm-arg=-march");
-    std::string Arg = "-plugin-opt=-lto-external-asm-arg=";
-    Arg += CPUName.data();
-    CmdArgs.push_back(Args.MakeArgString(Arg));
-    CmdArgs.push_back("-plugin-opt=-lto-external-asm-arg=-EL");
+    if (ToolChain.useIntegratedAs()) {
+      CmdArgs.push_back(Args.MakeArgString("--plugin-opt=-lto-external-asm="
+					   + D.ClangExecutable));
+      CmdArgs.push_back("--plugin-opt=-lto-external-asm-arg=-cc1as");
+      CmdArgs.push_back("--plugin-opt=-lto-external-asm-arg=-triple");
+      std::string Arg = "-plugin-opt=-lto-external-asm-arg=";
+      Arg += "nanomips-elf";
+      CmdArgs.push_back(Args.MakeArgString(Arg));
+      CmdArgs.push_back("--plugin-opt=-lto-external-asm-arg=-filetype");
+      Arg = "-plugin-opt=-lto-external-asm-arg=obj";
+      CmdArgs.push_back(Args.MakeArgString(Arg));
+      CmdArgs.push_back("--plugin-opt=-lto-external-asm-arg=-target-cpu");
+      Arg = "--plugin-opt=-lto-external-asm-arg=";
+      Arg += CPUName.data();
+      CmdArgs.push_back(Args.MakeArgString(Arg));
+    }
+    else {
+      CmdArgs.push_back(Args.MakeArgString("--plugin-opt=-lto-external-asm="
+					   + (getToolChain()
+					      .GetProgramPath("as"))));
+      CmdArgs.push_back("-plugin-opt=-lto-external-asm-arg=-march");
+      std::string Arg = "-plugin-opt=-lto-external-asm-arg=";
+      Arg += CPUName.data();
+      CmdArgs.push_back(Args.MakeArgString(Arg));
+      CmdArgs.push_back("-plugin-opt=-lto-external-asm-arg=-EL");
+      CmdArgs.push_back("-plugin-opt=-lto-external-asm-arg=-mlegacyregs");
+    }
   }
 
   if (Args.hasArg(options::OPT_Z_Xlinker__no_demangle))

clang/lib/Driver/ToolChains/NanoMips.h

@@ -50,11 +50,6 @@ class LLVM_LIBRARY_VISIBILITY NanoMips : public Generic_ELF {
     return true;
   }
 
-  bool useIntegratedAs() const override {
-    // No integrated assembler for NanoMips
-    return false;
-  }
-
 };
 
 } // toolchains

llvm/include/llvm/BinaryFormat/ELF.h

@@ -318,6 +318,7 @@ enum {
   EM_RISCV = 243,         // RISC-V
   EM_LANAI = 244,         // Lanai 32-bit processor
   EM_BPF = 247,           // Linux kernel bpf virtual machine
+  EM_NANOMIPS = 249,	  // MIPS Tech nanoMIPS architecture
   EM_VE = 251,            // NEC SX-Aurora VE
   EM_CSKY = 252,          // C-SKY 32-bit processor
 };
@@ -593,6 +594,38 @@ enum {
   ODK_PAGESIZE = 11   // Page size information
 };
 
+// ELF Relocation types for Mips
+enum {
+#include "ELFRelocs/NanoMips.def"
+};
+
+// NanoMips specific e_flags
+enum : unsigned {
+  // File may be relaxed by the linker.
+  EF_NANOMIPS_LINKRELAX = 0x00000001,
+  // File contains position independent code.
+  EF_NANOMIPS_PIC = 0x00000002,
+  // Indicates code compiled for a 64-bit machine in 32-bit mode
+  // (regs are 32-bits wide).
+  EF_NANOMIPS_32BITMODE = 0x00000004,
+  // Indicate that all data access in this object is GP-relative
+  EF_NANOMIPS_PID = 0x00000008,
+  // Indicate that this object does not use absolute addressing.
+  EF_NANOMIPS_PCREL = 0x00000010,
+  // Four bit nanoMIPS architecture field.
+  EF_NANOMIPS_ARCH = 0xf0000000,
+  // -march=32r6 code.
+  E_NANOMIPS_ARCH_32R6 = 0x00000000,
+  // -march=64r6 code.
+  E_NANOMIPS_ARCH_64R6 = 0x10000000,
+  // The ABI of the file.
+  EF_NANOMIPS_ABI = 0x0000f000,
+  // nanoMIPS ABI in 32 bit mode.
+  E_NANOMIPS_ABI_P32 = 0x00001000,
+  // nanoMIPS ABI in 64 bit mode.
+  E_NANOMIPS_ABI_P64 = 0x00002000
+};
+
 // Hexagon-specific e_flags
 enum {
   // Object processor version flags, bits[11:0]
@@ -970,6 +1003,8 @@ enum : unsigned {
   SHT_MIPS_DWARF = 0x7000001e,    // DWARF debugging section.
   SHT_MIPS_ABIFLAGS = 0x7000002a, // ABI information.
 
+  SHT_NANOMIPS_ABIFLAGS = 0x70000000, // ABI information.
+
   SHT_MSP430_ATTRIBUTES = 0x70000003U,
 
   SHT_RISCV_ATTRIBUTES = 0x70000003U,

llvm/include/llvm/BinaryFormat/ELFRelocs/NanoMips.def

@@ -0,0 +1,78 @@
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_NANOMIPS_NONE, 0)
+ELF_RELOC(R_NANOMIPS_32, 1)
+ELF_RELOC(R_NANOMIPS_64, 2)
+ELF_RELOC(R_NANOMIPS_NEG, 3)
+ELF_RELOC(R_NANOMIPS_ASHIFTR_1, 4)
+ELF_RELOC(R_NANOMIPS_UNSIGNED_8, 5)
+ELF_RELOC(R_NANOMIPS_SIGNED_8, 6)
+ELF_RELOC(R_NANOMIPS_UNSIGNED_16, 7)
+ELF_RELOC(R_NANOMIPS_SIGNED_16, 8)
+ELF_RELOC(R_NANOMIPS_RELATIVE, 9)
+ELF_RELOC(R_NANOMIPS_GLOBAL, 10)
+ELF_RELOC(R_NANOMIPS_JUMP_SLOT, 11)
+ELF_RELOC(R_NANOMIPS_IRELATIVE, 12)
+ELF_RELOC(R_NANOMIPS_PC25_S1, 13)
+ELF_RELOC(R_NANOMIPS_PC21_S1, 14)
+ELF_RELOC(R_NANOMIPS_PC14_S1, 15)
+ELF_RELOC(R_NANOMIPS_PC11_S1, 16)
+ELF_RELOC(R_NANOMIPS_PC10_S1, 17)
+ELF_RELOC(R_NANOMIPS_PC7_S1, 18)
+ELF_RELOC(R_NANOMIPS_PC4_S1, 19)
+ELF_RELOC(R_NANOMIPS_GPREL19_S2, 20)
+ELF_RELOC(R_NANOMIPS_GPREL18_S3, 21)
+ELF_RELOC(R_NANOMIPS_GPREL18, 22)
+ELF_RELOC(R_NANOMIPS_GPREL17_S1, 23)
+ELF_RELOC(R_NANOMIPS_GPREL16_S2, 24)
+ELF_RELOC(R_NANOMIPS_GPREL7_S2, 25)
+ELF_RELOC(R_NANOMIPS_GPREL_HI20, 26)
+ELF_RELOC(R_NANOMIPS_PCHI20, 27)
+ELF_RELOC(R_NANOMIPS_HI20, 28)
+ELF_RELOC(R_NANOMIPS_LO12, 29)
+ELF_RELOC(R_NANOMIPS_GPREL_I32, 30)
+ELF_RELOC(R_NANOMIPS_PC_I32, 31)
+ELF_RELOC(R_NANOMIPS_I32, 32)
+ELF_RELOC(R_NANOMIPS_GOT_DISP, 33)
+ELF_RELOC(R_NANOMIPS_GOTPC_I32, 34)
+ELF_RELOC(R_NANOMIPS_GOTPC_HI20, 35)
+ELF_RELOC(R_NANOMIPS_GOT_LO12, 36)
+ELF_RELOC(R_NANOMIPS_GOT_CALL, 37)
+ELF_RELOC(R_NANOMIPS_GOT_PAGE, 38)
+ELF_RELOC(R_NANOMIPS_GOT_OFST, 39)
+ELF_RELOC(R_NANOMIPS_LO4_S2, 40)
+ELF_RELOC(R_NANOMIPS_RESERVED1, 41)
+ELF_RELOC(R_NANOMIPS_GPREL_LO12, 42)
+ELF_RELOC(R_NANOMIPS_SCN_DISP, 43)
+ELF_RELOC(R_NANOMIPS_COPY, 44)
+ELF_RELOC(R_NANOMIPS_ALIGN, 64)
+ELF_RELOC(R_NANOMIPS_FILL, 65)
+ELF_RELOC(R_NANOMIPS_MAX, 66)
+ELF_RELOC(R_NANOMIPS_INSN32, 67)
+ELF_RELOC(R_NANOMIPS_FIXED, 68)
+ELF_RELOC(R_NANOMIPS_NORELAX, 69)
+ELF_RELOC(R_NANOMIPS_RELAX, 70)
+ELF_RELOC(R_NANOMIPS_SAVERESTORE, 71)
+ELF_RELOC(R_NANOMIPS_INSN16, 72)
+ELF_RELOC(R_NANOMIPS_JALR32, 73)
+ELF_RELOC(R_NANOMIPS_JALR16, 74)
+ELF_RELOC(R_NANOMIPS_JUMPTABLE_LOAD, 75)
+ELF_RELOC(R_NANOMIPS_FRAME_REG, 76)
+ELF_RELOC(R_NANOMIPS_NOTRAMP, 77)
+ELF_RELOC(R_NANOMIPS_TLS_DTPMOD, 80)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL, 81)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL, 82)
+ELF_RELOC(R_NANOMIPS_TLS_GD, 83)
+ELF_RELOC(R_NANOMIPS_TLS_GD_I32, 84)
+ELF_RELOC(R_NANOMIPS_TLS_LD, 85)
+ELF_RELOC(R_NANOMIPS_TLS_LD_I32, 86)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL12, 87)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL16, 88)
+ELF_RELOC(R_NANOMIPS_TLS_DTPREL_I32, 89)
+ELF_RELOC(R_NANOMIPS_TLS_GOTTPREL, 90)
+ELF_RELOC(R_NANOMIPS_TLS_GOTTPREL_PC_I32, 91)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL12, 92)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL16, 93)
+ELF_RELOC(R_NANOMIPS_TLS_TPREL_I32, 94)

llvm/include/llvm/IR/IntrinsicsMips.td

@@ -1781,4 +1781,7 @@ def int_mips_xor_v : GCCBuiltin<"__builtin_msa_xor_v">,
 
 def int_mips_xori_b : GCCBuiltin<"__builtin_msa_xori_b">,
   Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+
+def int_mips_hide: Intrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+
 }

llvm/include/llvm/MC/MCAsmInfo.h

@@ -224,6 +224,10 @@ class MCAsmInfo {
   /// still be lexed as a comment.
   bool AllowHashAtStartOfIdentifier = false;
 
+  /// This is true if the assembler allows the "[]" characters within an
+  /// identifier.
+  bool AllowBracInName = false;
+
   /// If this is true, symbol names with invalid characters will be printed in
   /// quotes.
   bool SupportsQuotedNames = true;
@@ -482,6 +486,10 @@ class MCAsmInfo {
   /// location is allowed.
   bool SupportsExtendedDwarfLocDirective = true;
 
+  /// True if the target uses compressed half-word instruction byte order.
+  /// This is true for NanoMips and Thumb2.
+  bool UsesCompInstByteOrder = false;
+
   //===--- Prologue State ----------------------------------------------===//
 
   std::vector<MCCFIInstruction> InitialFrameState;
@@ -683,6 +691,7 @@ class MCAsmInfo {
   bool doesAllowHashAtStartOfIdentifier() const {
     return AllowHashAtStartOfIdentifier;
   }
+  bool doesAllowBracInName() const { return AllowBracInName; }
   bool supportsNameQuoting() const { return SupportsQuotedNames; }
 
   bool doesSupportDataRegionDirectives() const {
@@ -855,6 +864,9 @@ class MCAsmInfo {
   bool hasMipsExpressions() const { return HasMipsExpressions; }
   bool needsFunctionDescriptors() const { return NeedsFunctionDescriptors; }
   bool shouldUseMotorolaIntegers() const { return UseMotorolaIntegers; }
+
+  /// True if the target uses compressed half-word instruction byte ordering.
+  bool usesCompInstByteOrder() const { return UsesCompInstByteOrder; }
 };
 
 } // end namespace llvm

llvm/include/llvm/MC/MCParser/MCAsmLexer.h

@@ -49,6 +49,7 @@ class MCAsmLexer {
   bool SkipSpace = true;
   bool AllowAtInIdentifier;
   bool AllowHashInIdentifier = false;
+  bool AllowBracInIdentifier =  false;
   bool IsAtStartOfStatement = true;
   bool LexMasmHexFloats = false;
   bool LexMasmIntegers = false;
@@ -153,6 +154,8 @@ class MCAsmLexer {
 
   void setAllowHashInIdentifier(bool V) { AllowHashInIdentifier = V; }
 
+  void setAllowBracInIdentifier(bool V) { AllowBracInIdentifier = V; }
+
   void setCommentConsumer(AsmCommentConsumer *CommentConsumer) {
     this->CommentConsumer = CommentConsumer;
   }

llvm/include/llvm/Support/MipsABIFlags.h

@@ -30,6 +30,7 @@ enum AFL_REG {
 // Masks for the ases word of an ABI flags structure.
 enum AFL_ASE {
   AFL_ASE_DSP = 0x00000001,       // DSP ASE
+  AFL_ASE_TLB = 0x00000001,	  // Re-uses above bit
   AFL_ASE_DSPR2 = 0x00000002,     // DSP R2 ASE
   AFL_ASE_EVA = 0x00000004,       // Enhanced VA Scheme
   AFL_ASE_MCU = 0x00000008,       // MCU (MicroController) ASE
@@ -43,7 +44,8 @@ enum AFL_ASE {
   AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
   AFL_ASE_XPA = 0x00001000,       // XPA ASE
   AFL_ASE_CRC = 0x00008000,       // CRC ASE
-  AFL_ASE_GINV = 0x00020000       // GINV ASE
+  AFL_ASE_GINV = 0x00020000,       // GINV ASE
+  AFL_ASE_xNMS = 0x00040000,       // not nanoMIPS Subset
 };
 
 // Values for the isa_ext word of an ABI flags structure.

llvm/include/llvm/module.modulemap

@@ -72,6 +72,7 @@ module LLVM_BinaryFormat {
     textual header "BinaryFormat/ELFRelocs/Lanai.def"
     textual header "BinaryFormat/ELFRelocs/M68k.def"
     textual header "BinaryFormat/ELFRelocs/Mips.def"
+    textual header "BinaryFormat/ELFRelocs/NanoMips.def"
     textual header "BinaryFormat/ELFRelocs/MSP430.def"
     textual header "BinaryFormat/ELFRelocs/PowerPC64.def"
     textual header "BinaryFormat/ELFRelocs/PowerPC.def"

llvm/include/mtk/tool_copyright.h

@@ -0,0 +1,11 @@
+/* Copyright (C) 2024 MediaTek Inc. All Rights Reserved. */
+
+/* define a version string macro COPYRIGHT that can be linked into 
+   any of the compiler tools that we supply */
+
+#define TOOL_COPYRIGHT \
+   "  Copyright (c) 2020-2024 MediaTek Inc. All Rights Reserved.\n" \
+   "  See the file COPYRIGHT for usage terms and additional copyrights.\n"
+
+/* end of file */
+

llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp

@@ -45,6 +45,12 @@ using namespace llvm;
 
 #define DEBUG_TYPE "dwarfdebug"
 
+
+static cl::opt<bool> ShareDebugAcrossCUs(
+    "share-debug-across-cus", cl::Hidden,
+    cl::desc("Share DWARF debug entries across CUs in output DWARF"), cl::init(true));
+
+
 DIEDwarfExpression::DIEDwarfExpression(const AsmPrinter &AP,
                                        DwarfCompileUnit &CU, DIELoc &DIE)
     : DwarfExpression(AP.getDwarfVersion(), CU), AP(AP), OutDIE(DIE) {}
@@ -186,6 +192,8 @@ int64_t DwarfUnit::getDefaultLowerBound() const {
 
 /// Check whether the DIE for this MDNode can be shared across CUs.
 bool DwarfUnit::isShareableAcrossCUs(const DINode *D) const {
+  if (!ShareDebugAcrossCUs)
+    return false;
   // When the MDNode can be part of the type system, the DIE can be shared
   // across CUs.
   // Combining type units and cross-CU DIE sharing is lower value (since

llvm/lib/LTO/LTOBackend.cpp

@@ -454,12 +454,12 @@ void assemble(const Config &Conf, TargetMachine *TM, AddStreamFn AddStream,
   Assembler.append(LtoExternalAsm);
   std::vector<StringRef> Args;
   Args.push_back(Assembler);
-  Args.push_back(AsmFileName);
-  Args.push_back("-o");
-  Args.push_back(DojFileName);
   for ( auto &A : LtoExternalAsmArgs ) {
     Args.push_back(A);
   }
+  Args.push_back(AsmFileName);
+  Args.push_back("-o");
+  Args.push_back(DojFileName);
 
   LLVM_DEBUG(dbgs() << "Run assembler on module " << Mod.getModuleIdentifier()
                     << "\n");