Problem 1 : Design an 8 bit full adder using 1 bit full adder modules and add these two binary numbers: 8’b10110101 and 8’b10100111
Note: You have to generate the RTL schematic of the adder.
Problem 2: Design a 4 to 2 priority encoder (0>1>3>2) using Verilog HDL and verify using timing diagram.
Note: Show and discuss the case when multiple input bits are high.