Skip to content

Commit

Permalink
area(LoadQueueReplay): optimise exceptionVec(loadAddrMisaligned)
Browse files Browse the repository at this point in the history
  • Loading branch information
jin120811 committed Oct 29, 2024
1 parent a592590 commit 0ca72f2
Showing 1 changed file with 1 addition and 0 deletions.
1 change: 1 addition & 0 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
Original file line number Diff line number Diff line change
Expand Up @@ -535,6 +535,7 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
replay_req(i).valid := s2_oldestSel(i).valid
replay_req(i).bits := DontCare
replay_req(i).bits.uop := s2_replayUop
replay_req(i).bits.uop.exceptionVec(loadAddrMisaligned) := false.B
replay_req(i).bits.isvec := s2_vecReplay.isvec
replay_req(i).bits.isLastElem := s2_vecReplay.isLastElem
replay_req(i).bits.is128bit := s2_vecReplay.is128bit
Expand Down

0 comments on commit 0ca72f2

Please sign in to comment.