fix(CSR): correct the width of PC pgaddr for inst fetch exception #3795
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[Generated by IPC robot]
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[Generated by IPC robot]
master branch:
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We found that the CSR mtval2 truncates the high bits of gpaddr when GPF occurs in instruction fetching. Actually, there is an GPAMem which storages the whole 64-bit gpaddr, but it does not pass to CSR correctly, due to incorrect width of trapPCGPA in module NewCSR and bundle TrapEntryEventInput. This patch fixes this.
The paddr genereted by VS Stage could only be 56 bits. So we could reduce the datapath width of IGPF tval2. Besides, tval2/gpaddr could be over 56 bits only when an jump occurs and only G stage is enabled. This is handled by backend and not use this datapath.
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We found that the CSR mtval2 truncates the high bits of gpaddr when GPF occurs in instruction fetching. Actually, there is an GPAMem which storages the whole 64-bit gpaddr, but it does not pass to CSR correctly, due to incorrect width of trapPCGPA in module NewCSR and bundle TrapEntryEventInput. This patch fixes this.