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fix(CSR): correct the width of PC pgaddr for inst fetch exception #3795

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fix(CSR): correct the width of PC pgaddr for inst fetch exception #3795

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Commits on Nov 12, 2024

  1. fix(CSR): correct the width of PC pgaddr for inst fetch exception 

    We found that the CSR mtval2 truncates the high bits of gpaddr when GPF occurs in instruction fetching. Actually, there is an GPAMem which storages the whole 64-bit gpaddr, but it does not pass to CSR correctly, due to incorrect width of trapPCGPA in module NewCSR and bundle TrapEntryEventInput. This patch fixes this.
    @cebarobot
    cebarobot committed Nov 12, 2024
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  2. feat(CSR): reduce the bit width of exception gpaddr 

    The paddr genereted by VS Stage could only be 56 bits. So we could reduce the datapath width of IGPF tval2.

Besides, tval2/gpaddr could be over 56 bits only when an jump occurs and only G stage is enabled. This is handled by backend and not use this datapath.
    @cebarobot
    cebarobot committed Nov 12, 2024
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  3. fix(ICache,IFU): increase gpaddr to PAddrBitsMax(56bit)

    @ngc7331 @cebarobot
    ngc7331 authored and cebarobot committed Nov 12, 2024
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