Actions: UCSBarchlab/PyRTL
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initialize_registers
option to output_to_verilog
.
Run Python tests
#28:
Commit 0424a70
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initialize_registers
option to output_to_verilog
.
Build and publish release
#25:
Commit 0424a70
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signed_*
Build and publish release
#19:
Commit b542881
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signed_*
Run Python tests
#21:
Commit b542881
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fdxmw