Support negative Inputs in CompiledSimulation. Also:

- Use `infer_val_and_bitwidth` for all input checks in Simulation and FastSimulation
- Add {} as a default argument to Simulation.step()
- Minor documentation improvements in helperfuncs.py

docs/helpers.rst

@@ -63,6 +63,8 @@ reasoning about bit vector representations of human understandable values.
 .. autofunction:: pyrtl.helperfuncs.val_to_signed_integer
 .. autofunction:: pyrtl.helperfuncs.val_to_formatted_str
 .. autofunction:: pyrtl.helperfuncs.formatted_str_to_val
+.. autoclass:: pyrtl.helperfuncs.ValueBitwidthTuple
+   :members: value, bitwidth
 .. autofunction:: pyrtl.helperfuncs.infer_val_and_bitwidth
 .. autofunction:: pyrtl.helperfuncs.log2
 

docs/requirements.txt

@@ -32,7 +32,7 @@ pygments==2.18.0
     # via
     #   furo
     #   sphinx
-requests==2.32.0
+requests==2.32.3
     # via sphinx
 snowballstemmer==2.2.0
     # via sphinx

examples/example2-counter.py

@@ -77,6 +77,6 @@ def ripple_add(a, b, carry_in=0):
 sim_trace = pyrtl.SimulationTrace()
 sim = pyrtl.Simulation(tracer=sim_trace)
 for cycle in range(15):
-    sim.step({})
+    sim.step()
     assert sim.value[counter] == cycle % 8
 sim_trace.render_trace()

pyrtl/compilesim.py

@@ -14,6 +14,7 @@
 from .memory import MemBlock, RomBlock
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
 from .simulation import SimulationTrace, _trace_sort_key
+from .helperfuncs import infer_val_and_bitwidth
 
 try:
     from collections.abc import Mapping
@@ -152,10 +153,11 @@ def inspect(self, w: str) -> int:
             return vals[-1]
         raise PyrtlError('CompiledSimulation does not support inspecting internal WireVectors')
 
-    def step(self, inputs: dict[str, int]):
+    def step(self, provided_inputs: dict[str, int] = {}, inputs=None):
         """Run one step of the simulation.
 
-        :param inputs: A mapping from input names to the values for the step.
+        :param provided_inputs: A mapping from input names to the values for
+            the step.
 
         A step causes the block to be updated as follows, in order:
 
@@ -166,8 +168,15 @@ def step(self, inputs: dict[str, int]):
         3. Memories are updated
         4. The :attr:`~.Register.next` values of the registers are saved for
            use in step 1 of the next cycle.
+
         """
-        self.run([inputs])
+        if inputs is not None:
+            import warnings
+            warnings.warn(
+                'CompiledSimulation.step: `inputs` was renamed to '
+                '`provided_inputs`', DeprecationWarning)
+            provided_inputs = inputs
+        self.run([provided_inputs])
 
     def step_multiple(self, provided_inputs: dict[str, list[int]] = {},
                       expected_outputs: dict[str, int] = {},
@@ -317,6 +326,8 @@ def run(self, inputs: list[dict[str, int]]):
                 start, count = self._inputpos[name]
                 start += n * self._ibufsz
                 val = inmap[w]
+                val = infer_val_and_bitwidth(
+                    val, bitwidth=self._inputbw[name]).value
                 if val >= 1 << self._inputbw[name]:
                     raise PyrtlError(
                         'Wire {} has value {} which cannot be represented '