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Fix: RISC-V vs ENABLE_DEBUG=1 #1668

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merged 2 commits into from
Nov 13, 2023
Merged

Fix: RISC-V vs ENABLE_DEBUG=1 #1668

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6d7b0db
jtag_devs: Fix the logic around the RISC-V debug entry so it gets ena…
dragonmux Nov 2, 2023
cadc36d
stm32f1: Improved the hygene of when gd32vf1_probe() gets defined so …
dragonmux Nov 2, 2023
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6 changes: 5 additions & 1 deletion src/target/jtag_devs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -348,13 +348,17 @@ const jtag_dev_descr_s dev_descr[] = {
.ir_value = 1U,
},
},
#ifdef ENABLE_DEBUG
#ifdef ENABLE_RISCV
{
.idcode = 0x0000563dU,
.idmask = 0x0fffffffU,
#ifdef ENABLE_DEBUG
.descr = "RISC-V debug v0.13.",
#endif
.handler = riscv_jtag_dtm_handler,
},
#endif
#ifdef ENABLE_DEBUG
{
.idcode = 0x000007a3U,
.idmask = 0x00000fffU,
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2 changes: 2 additions & 0 deletions src/target/stm32f1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -182,6 +182,7 @@ bool gd32f1_probe(target_s *target)
return true;
}

#ifdef ENABLE_RISCV
/* Identify RISC-V GD32VF1 chips */
bool gd32vf1_probe(target_s *const target)
{
Expand Down Expand Up @@ -210,6 +211,7 @@ bool gd32vf1_probe(target_s *const target)

return true;
}
#endif

static bool at32f40_detect(target_s *target, const uint16_t part_id)
{
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