Add i3c-core RTL code

Hardcode it for now at 0xD000_0000. Signed-off-by: Arthur Heymans <[email protected]>
chipsalliance · Oct 16, 2024 · 8b5e2bb · 8b5e2bb
1 parent 5b8dc85
commit 8b5e2bb
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diff --git a/.gitmodules b/.gitmodules
@@ -9,3 +9,6 @@
 	path = dpe
 	url = https://github.com/chipsalliance/caliptra-dpe.git
 	branch = main
+[submodule "hw/latest/i3c-core-rtl"]
+	path = hw/latest/i3c-core-rtl
+	url = https://github.com/chipsalliance/i3c-core.git
diff --git a/hw/latest/i3c-core-rtl b/hw/latest/i3c-core-rtl