Skip to content

Pull requests: chipsalliance/fpga-interchange-tests

New pull request New
8 Open 94 Closed
8 Open 94 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Add UHDM/SystemVerilog support and test
#129 opened Aug 4, 2022 by kboronski-ant Loading…
[BOT] Conda Lock Update bot-conda-lock-update merge-if-green Merge pull request if the CI system goes green
#116 opened Jul 6, 2022 by github-actions bot Loading…
tests: zcu104: add murax test
#109 opened Mar 23, 2022 by acomodi Loading…
1
Feature tests for Ultrascale+ (failing due to no route)
#96 opened Feb 25, 2022 by kboronski-ant Loading…
tests: remove retarget from LiteX tests
#89 opened Dec 3, 2021 by acomodi Loading…
LUT-thru tests
#87 opened Nov 29, 2021 by mkurc-ant Loading…
16
GH action: add conda bot lock
#86 opened Nov 26, 2021 by acomodi Loading…
xcup: Enable global clock routing
#53 opened Jul 20, 2021 by gatecat Loading…
ProTip! no:milestone will show everything without a milestone.