Merge pull request #124 from antmicro/fix_timing_comparasion

Fix backslash escape by converting any series of them into single backslash
chipsalliance · Sep 23, 2021 · 7a9d020 · 7a9d020
2 parents 4d5af81 + 0c7eae6
commit 7a9d020
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/fpga_interchange/compare_timings.py b/fpga_interchange/compare_timings.py
@@ -17,6 +17,7 @@
 
 import argparse
 import sys
+import re
 
 # ============================================================================
 
@@ -50,12 +51,16 @@ def main():
     with open(args.base_timing, 'r') as f:
         for line in f.readlines():
             line = line.split()
+            line[0] = re.sub(r"\\\\*", '\\', line[0])
+            print(line[0])
             baseline[line[0]] = int(float(line[1]))
 
     comp = {}
     with open(args.compare_timing, 'r') as f:
         for line in f.readlines():
             line = line.split()
+            line[0] = re.sub(r"\\\\*", '\\', line[0])
+            print(line[0])
             comp[line[0]] = int(float(line[1]))
 
     map_net = {}