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Fix CSR test generation for RV64 #987

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serge0699 wants to merge 1 commit into chipsalliance:master from serge0699:master

serge0699 commented Jul 9, 2024 •

edited

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Before this commit only 32 of 64 bits were randomized for random value written to CSR.


          Fix CSR test generation for RV64

f3e4599

Before this commit only 32 of 64 were randomized for random value written to CSR.

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