[plic] full implementation #2

Lucas-Wye · 2024-09-12T08:05:33Z

No description provided.

sequencer · 2024-09-12T11:26:31Z

plic/src/PLIC.scala

+class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
+  val io = IO(new Bundle {
+    val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
+    val ip   = Flipped(UInt(nDevices.W))
+    val dev  = UInt(log2Ceil(nDevices+1).W)
+    val max  = UInt(prioBits.W)
+  })
+
+  def findMax(x: Seq[UInt]): (UInt, UInt) = {
+    if (x.length > 1) {
+      val half = 1 << (log2Ceil(x.length) - 1)
+      val left = findMax(x take half)
+      val right = findMax(x drop half)
+      MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
+    } else (x.head, 0.U)
+  }
+
+  val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
+  val (maxPri, maxDev) = findMax(effectivePriority)
+  io.max := maxPri // strips the always-constant high '1' bit
+  io.dev := maxDev
+}
+


please inline this module

sequencer · 2024-09-12T11:27:28Z

plic/src/PLIC.scala

  val plic = Flipped(axi4.bundle.verilog.irrevocable(parameter.axi4parameter)).asInstanceOf[AXI4RWIrrevocableVerilog]
  val source = Input(Vec(parameter.sources, Bool()))
-  val mip = Output(Vec(parameter.harts, Bool()))
-  val sip = Output(Vec(parameter.harts, Bool()))
+  val ip = Output(Vec(parameter.harts, Bool()))


Suggested change

val ip = Output(Vec(parameter.harts, Bool()))

val ip = Output(Vec(parameter.contexts, Bool()))

sequencer

And remember reformat.

sequencer · 2024-09-16T14:35:22Z

plic/src/PLIC.scala

+  val priority = if (parameter.nPriorities > 0) Seq.tabulate(parameter.nDevices)(idx => Reg(UInt(parameter.prioBits.W)))
+    else Seq.tabulate(parameter.nDevices max 1)(idx => WireDefault(1.U))
+  val threshold = if (parameter.nPriorities > 0) Seq.tabulate(parameter.nHarts)(idx => Reg(UInt(parameter.prioBits.W)))
+    else Seq.tabulate(parameter.nHarts)(idx => Reg(0.U))


Add suggest name for each.

sequencer · 2024-09-17T00:39:44Z

plic/src/PLIC.scala

+  val firstEnable = parameter.nDevices min 7
+  val fullEnables = (parameter.nDevices - firstEnable) / 8
+  val tailEnable  = parameter.nDevices - firstEnable - 8*fullEnables


move these into parameter.

sequencer · 2024-09-17T00:40:55Z

plic/src/PLIC.scala

+  class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
+    val io = IO(new Bundle {
+      val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
+      val ip   = Flipped(UInt(nDevices.W))
+      val dev  = UInt(log2Ceil(nDevices+1).W)
+      val max  = UInt(prioBits.W)
+    })
+
+    def findMax(x: Seq[UInt]): (UInt, UInt) = {
+      if (x.length > 1) {
+        val half = 1 << (log2Ceil(x.length) - 1)
+        val left = findMax(x take half)
+        val right = findMax(x drop half)
+        MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
+      } else (x.head, 0.U)
+    }
+
+    val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
+    val (maxPri, maxDev) = findMax(effectivePriority)
+    io.max := maxPri // strips the always-constant high '1' bit
+    io.dev := maxDev
+  }


Don't use Module here, just move the logic out.

sequencer · 2024-09-17T00:41:36Z

plic/src/PLIC.scala

+
+  if(parameter.nDevices > 0) {
+    for (hart <- 0 until parameter.nHarts) {
+      val fanin = Module(new PLICFanIn(parameter.nDevices, parameter.prioBits))


Don't use Module here, just move the logic out.

sequencer · 2024-09-17T00:41:47Z

plic/src/PLIC.scala

+  }
+
+  if(parameter.nDevices > 0) {
+    for (hart <- 0 until parameter.nHarts) {


Use Seq.tabulate

sequencer · 2024-09-17T00:42:37Z

plic/src/PLIC.scala

+  def priorityRegField(x: UInt, i: Int) =
+    if (parameter.nPriorities > 0) {
+      RegField(parameter.prioBits, x, priorityRegDesc(i))
+    } else {
+      RegField.r(parameter.prioBits, x, priorityRegDesc(i))
+    }


Since only one place use it, you can inline it.

sequencer · 2024-09-17T00:43:58Z

plic/src/PLIC.scala

+  // were to change, it may no longer be true.
+  // Note -- PLIC doesn't care which hart writes the register.  
+  val completer = Wire(Vec(parameter.nHarts, Bool()))
+  assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot


Suggested change

assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot

assert(PopCount(completer.asUInt) <= 1.U) // One-Hot

sequencer · 2024-09-17T00:47:24Z

plic/src/PLIC.scala

  def nHarts = harts
+  def contexts = harts


remove the usage of nHarts, harts and nDevices

sequencer · 2024-09-17T00:51:41Z

plic/src/PLIC.scala

+    def findMax(x: Seq[UInt]): (UInt, UInt) = {
+      if (x.length > 1) {
+        val half = 1 << (log2Ceil(x.length) - 1)
+        val left = findMax(x take half)
+        val right = findMax(x drop half)
+        MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
+      } else (x.head, 0.U)
+    }


I personally refer using DW_minmax, but it can be left the future PR.

sequencer · 2024-09-17T00:53:05Z

plic/src/PLIC.scala

+  def thresholdRegField(x: UInt, i: Int) =
+    if (parameter.nPriorities > 0) {
+      RegField(parameter.prioBits, x, thresholdRegDesc(i))
+    } else {
+      RegField.r(parameter.prioBits, x, thresholdRegDesc(i))
+    }


Just inline this function.

sequencer

Please inline the Module.

sequencer · 2024-09-17T10:38:49Z

plic/src/PLIC.scala

+    class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
+      val io = IO(new Bundle {
+        val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
+        val ip = Flipped(UInt(nDevices.W))
+        val dev = UInt(log2Ceil(nDevices + 1).W)
+        val max = UInt(prioBits.W)
+      })


Please inline the PLICFanIn Module to provide as simple as possible logic, in traditional Verilog, it should be a function. In chisel, we use an inline Module to provide this feature, however the biggest issue was module linking.
The purpose of rocket-uncore is designed to provide an as simple as possible elaborator for the RISC-V related bus ips. For downstream users of the rocket-uncore, they only need to define the config and get the Verilog+IP-XACT for SoC design, thus minimizing the Module number to simplify the linking burden need to be concerned.

Lucas-Wye force-pushed the dev-plic branch from d7c8fc6 to 3d839bc Compare September 12, 2024 10:23

sequencer reviewed Sep 12, 2024

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Lucas-Wye force-pushed the dev-plic branch from 3d839bc to d464e11 Compare September 16, 2024 02:45

sequencer requested changes Sep 17, 2024

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Lucas-Wye force-pushed the dev-plic branch from d464e11 to e841148 Compare September 17, 2024 03:29

sequencer requested changes Sep 17, 2024

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Lucas-Wye force-pushed the dev-plic branch from e841148 to 2b909f4 Compare September 17, 2024 14:14

sequencer approved these changes Sep 17, 2024

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[plic] full implementation

289130c

Lucas-Wye force-pushed the dev-plic branch from 2b909f4 to 289130c Compare September 29, 2024 07:20

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[plic] full implementation #2

[plic] full implementation #2

Lucas-Wye commented Sep 12, 2024

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sequencer Sep 17, 2024

	val ip = Output(Vec(parameter.harts, Bool()))
	val ip = Output(Vec(parameter.contexts, Bool()))

	assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
	assert(PopCount(completer.asUInt) <= 1.U) // One-Hot

[plic] full implementation #2

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[plic] full implementation #2

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