Package import fix for synlig #5953

Job	Run time
Build Synlig Release	5m 21s
Build Plugin	4m 45s
Build Synlig (ASAN)	8m 53s
Build Package	5m 0s
Build PySynlig	9m 35s
Build tools	10m 59s
Emit Workflow Info	0s
Style check	1m 41s
Verify README Correctness (Installation From Sources)	40m 45s
Parsing Tests / Test read_systemverilog release	4m 45s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 36s
Parsing Tests / Test read_uhdm release	4m 40s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 19s
Large Designs Tests / Ibex (Vivado synthesis)	6m 31s
Parsing Tests / Test read_systemverilog plugin	4m 45s
Parsing Tests / Test read_uhdm plugin	4m 27s
Parsing Tests / Test read_systemverilog asan	39m 26s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	38m 15s
Large Designs Tests / Black Parrot (ASIC synthesis)	45m 15s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	17m 7s
Parsing Tests / Test read_uhdm asan	25m 2s
Large Designs Tests / Opentitan parsing (full/top-down)	13m 20s
Large Designs Tests / Opentitan (synthesis)	57m 19s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 13s
Large Designs Tests / Opentitan parsing (quick)	6m 25s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	41m 28s
Formal Verification Tests / simple	18m 45s
Formal Verification Tests / sv2v	17m 29s
Formal Verification Tests / yosys	14m 36s
Parsing Tests / Summary Generation	1m 35s
Parsing Tests / Generate AST diff	0s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 51m 17s

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