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cleanup of playback
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Comma Device committed Sep 3, 2024
1 parent 3af1ea6 commit 4634d18
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101 changes: 35 additions & 66 deletions board/drivers/sound.h
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Original file line number Diff line number Diff line change
@@ -1,43 +1,51 @@

const uint8_t sine[360] = { 127U, 129U, 131U, 133U, 135U, 138U, 140U, 142U, 144U, 146U, 149U, 151U, 153U, 155U, 157U, 159U, 161U, 164U, 166U, 168U, 170U, 172U, 174U, 176U, 178U, 180U, 182U, 184U, 186U, 188U, 190U, 192U, 194U, 196U, 197U, 199U, 201U, 203U, 205U, 206U, 208U, 210U, 211U, 213U, 215U, 216U, 218U, 219U, 221U, 222U, 224U, 225U, 227U, 228U, 229U, 230U, 232U, 233U, 234U, 235U, 236U, 238U, 239U, 240U, 241U, 242U, 242U, 243U, 244U, 245U, 246U, 247U, 247U, 248U, 249U, 249U, 250U, 250U, 251U, 251U, 252U, 252U, 252U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 253U, 252U, 252U, 252U, 251U, 251U, 250U, 250U, 249U, 249U, 248U, 247U, 247U, 246U, 245U, 244U, 243U, 243U, 242U, 241U, 240U, 239U, 238U, 237U, 235U, 234U, 233U, 232U, 231U, 229U, 228U, 227U, 225U, 224U, 222U, 221U, 219U, 218U, 216U, 215U, 213U, 212U, 210U, 208U, 207U, 205U, 203U, 201U, 199U, 198U, 196U, 194U, 192U, 190U, 188U, 186U, 184U, 182U, 180U, 178U, 176U, 174U, 172U, 170U, 168U, 166U, 164U, 162U, 160U, 157U, 155U, 153U, 151U, 149U, 147U, 144U, 142U, 140U, 138U, 136U, 133U, 131U, 129U, 127U, 124U, 122U, 120U, 118U, 116U, 113U, 111U, 109U, 107U, 105U, 102U, 100U, 98U, 96U, 94U, 92U, 90U, 87U, 85U, 83U, 81U, 79U, 77U, 75U, 73U, 71U, 69U, 67U, 65U, 63U, 61U, 59U, 58U, 56U, 54U, 52U, 50U, 49U, 47U, 45U, 43U, 42U, 40U, 38U, 37U, 35U, 34U, 32U, 31U, 29U, 28U, 27U, 25U, 24U, 23U, 21U, 20U, 19U, 18U, 17U, 16U, 14U, 13U, 12U, 12U, 11U, 10U, 9U, 8U, 7U, 7U, 6U, 5U, 4U, 4U, 3U, 3U, 2U, 2U, 1U, 1U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 1U, 1U, 2U, 2U, 3U, 3U, 4U, 4U, 5U, 6U, 6U, 7U, 8U, 9U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 19U, 20U, 21U, 22U, 24U, 25U, 26U, 28U, 29U, 30U, 32U, 33U, 35U, 36U, 38U, 40U, 41U, 43U, 45U, 46U, 48U, 50U, 52U, 53U, 55U, 57U, 59U, 61U, 63U, 65U, 67U, 69U, 70U, 72U, 74U, 77U, 79U, 81U, 83U, 85U, 87U, 89U, 91U, 93U, 95U, 98U, 100U, 102U, 104U, 106U, 108U, 111U, 113U, 115U, 117U, 119U, 122U, 124U };

// 16bit, 48kHz, stereo, 0.04s buffers
// TODO: also double-buffer TX
#define RX_BUF_SIZE 2000U
struct sound_buf_t {
uint16_t buf[RX_BUF_SIZE];
bool processed;
} sound_buf_t;

__attribute__((section(".sram4"))) struct sound_buf_t rx_buf[2];
__attribute__((section(".sram4"))) uint16_t buf[RX_BUF_SIZE];
__attribute__((section(".sram4"))) uint16_t rx_buf[2][RX_BUF_SIZE];
__attribute__((section(".sram4"))) uint16_t tx_buf[RX_BUF_SIZE];

void BDMA_Channel0_IRQ_Handler(void) {
BDMA->IFCR |= BDMA_IFCR_CGIF0; // clear flag
// print("sound dma interrupt\n");

// process samples (shift to 12b and bias to be unsigned)
uint8_t buf_idx = ((BDMA_Channel0->CCR & BDMA_CCR_CT) >> BDMA_CCR_CT_Pos) == 1U ? 0U : 1U;
for (uint16_t i=0U; i < RX_BUF_SIZE; i++) {
//buf[i] = (((int16_t *) rx_buf[buf_idx].buf)[i] >> 4) + 0x800;
// rx_buf[buf_idx].buf[i] = ((rx_buf[buf_idx].buf[i] & 0xFF) << 8) | ((rx_buf[buf_idx].buf[i] & 0xFF00) >> 8);

// buf[i] = (rx_buf[buf_idx].buf[i] >> 4) & 0xFFF;

int32_t biased = ((int32_t) ((int16_t *) rx_buf[buf_idx].buf)[i]) + (1U << 14);
biased &= 0xFFFF;

buf[i] = (((uint32_t) biased) >> 3);
tx_buf[i] = ((((int32_t) rx_buf[buf_idx][i]) + (1U << 14)) >> 3);
}

rx_buf[buf_idx].processed = true;
DMA1->LIFCR |= 0xFFFFFFFF;
register_clear_bits(&DMA1_Stream1->CR, DMA_SxCR_EN);
register_set(&DMA1_Stream1->M0AR, (uint32_t) buf, 0xFFFFFFFFU);
DMA1_Stream1->CR &= ~DMA_SxCR_EN;
register_set(&DMA1_Stream1->M0AR, (uint32_t) tx_buf, 0xFFFFFFFFU);
DMA1_Stream1->NDTR = RX_BUF_SIZE;
register_set_bits(&DMA1_Stream1->CR, DMA_SxCR_EN);
DMA1_Stream1->CR |= DMA_SxCR_EN;
}

void sai4_init(void) {
void sound_init(void) {
REGISTER_INTERRUPT(BDMA_Channel0_IRQn, BDMA_Channel0_IRQ_Handler, 64U, FAULT_INTERRUPT_RATE_SOUND_DMA)

// Init DAC
register_set(&DAC1->MCR, 0U, 0xFFFFFFFFU);
register_set(&DAC1->CR, DAC_CR_TEN1 | (6U << DAC_CR_TSEL1_Pos) | DAC_CR_DMAEN1, 0xFFFFFFFFU);
register_set_bits(&DAC1->CR, DAC_CR_EN1);

// Setup DMAMUX (DAC_CH1_DMA as input)
register_set(&DMAMUX1_Channel1->CCR, 67U, DMAMUX_CxCR_DMAREQ_ID_Msk);

// Setup DMA
register_set(&DMA1_Stream1->PAR, (uint32_t) &(DAC1->DHR12R1), 0xFFFFFFFFU);
register_set(&DMA1_Stream1->FCR, 0U, 0x00000083U);
DMA1_Stream1->CR = (0b11 << DMA_SxCR_PL_Pos) | (0b01 << DMA_SxCR_MSIZE_Pos) | (0b01 << DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | (1 << DMA_SxCR_DIR_Pos);

// Init trigger timer (48kHz)
register_set(&TIM7->PSC, 0U, 0xFFFFU);
register_set(&TIM7->ARR, 1247U, 0xFFFFU);
register_set(&TIM7->CR2, (0b10 << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk);
register_set(&TIM7->CR1, TIM_CR1_ARPE | TIM_CR1_URS, 0x088EU);
TIM7->SR = 0U;
TIM7->CR1 |= TIM_CR1_CEN;

register_set(&SAI4->GCR, 0U, SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk);

// stereo audio in (needs to be combined in fw, or set to mono on the host side)
Expand All @@ -47,16 +55,16 @@ void sai4_init(void) {
register_set(&SAI4_Block_B->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague

// mono mic out
register_set(&SAI1->PDMCR, (0b1 << SAI_PDMCR_CKEN2_Pos) | (0b00 << SAI_PDMCR_MICNBR_Pos) | (0b1 << SAI_PDMCR_PDMEN_Pos), 0x331);
register_set(&SAI4_Block_A->CR1, (0b01 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b10 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU);
register_set(&SAI4_Block_A->CR2, 0U, 0xFFFBU); // TODO: mute detection?
register_set(&SAI4_Block_A->CR2, 0U, 0xFFFBU);
register_set(&SAI4_Block_A->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU);
register_set(&SAI4_Block_A->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague
register_set(&SAI4->PDMCR, (0b1 << SAI_PDMCR_CKEN2_Pos) | (0b00 << SAI_PDMCR_MICNBR_Pos) | (0b1 << SAI_PDMCR_PDMEN_Pos), 0x331);

// init DMA (SAI4_B -> memory, double buffers)
register_set(&BDMA_Channel0->CPAR, (uint32_t) &(SAI4_Block_B->DR), 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM0AR, (uint32_t) rx_buf[0].buf, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM1AR, (uint32_t) rx_buf[1].buf, 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM0AR, (uint32_t) rx_buf[0], 0xFFFFFFFFU);
register_set(&BDMA_Channel0->CM1AR, (uint32_t) rx_buf[1], 0xFFFFFFFFU);
BDMA_Channel0->CNDTR = RX_BUF_SIZE;
register_set(&BDMA_Channel0->CCR, BDMA_CCR_DBM | (0b01 << BDMA_CCR_MSIZE_Pos) | (0b01 << BDMA_CCR_PSIZE_Pos) | BDMA_CCR_MINC | BDMA_CCR_CIRC | BDMA_CCR_TCIE, 0xFFFFU);
register_set(&DMAMUX2_Channel0->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_B_DMA
Expand All @@ -65,44 +73,5 @@ void sai4_init(void) {
// enable all initted blocks
register_set_bits(&SAI4_Block_A->CR1, SAI_xCR1_SAIEN);
register_set_bits(&SAI4_Block_B->CR1, SAI_xCR1_SAIEN);
}

void sound_init(void) {
// Init DAC
register_set(&DAC1->MCR, 0U, 0xFFFFFFFFU);
register_set(&DAC1->CR, DAC_CR_TEN1 | (6U << DAC_CR_TSEL1_Pos) | DAC_CR_DMAEN1, 0xFFFFFFFFU);
register_set_bits(&DAC1->CR, DAC_CR_EN1);

// Setup DMAMUX (DAC_CH1_DMA as input)
register_set(&DMAMUX1_Channel1->CCR, 67U, DMAMUX_CxCR_DMAREQ_ID_Msk);

// Setup DMA
register_set(&DMA1_Stream1->PAR, (uint32_t) &(DAC1->DHR12R1), 0xFFFFFFFFU);
register_set(&DMA1_Stream1->FCR, 0U, 0x00000083U);
DMA1_Stream1->CR = (0b11 << DMA_SxCR_PL_Pos) | (0b01 << DMA_SxCR_MSIZE_Pos) | (0b01 << DMA_SxCR_PSIZE_Pos) | DMA_SxCR_MINC | (1 << DMA_SxCR_DIR_Pos);
//DMA1_Stream1->CR |= DMA_SxCR_MINC | DMA_SxCR_CIRC | (1 << DMA_SxCR_DIR_Pos);
// register_set_bits(&DMA1_Stream1->CR, DMA_SxCR_EN);

// Setup DMA
// register_set(&DMA1_Stream1->M0AR, (uint32_t) sine, 0xFFFFFFFFU);
// register_set(&DMA1_Stream1->PAR, (uint32_t) &(DAC1->DHR8R1), 0xFFFFFFFFU);
// DMA1_Stream1->NDTR = sizeof(sine);
// register_set(&DMA1_Stream1->FCR, 0U, 0x00000083U);
// DMA1_Stream1->CR = (0b11UL << DMA_SxCR_PL_Pos);
// DMA1_Stream1->CR |= DMA_SxCR_MINC | DMA_SxCR_CIRC | (1U << DMA_SxCR_DIR_Pos);
// register_set_bits(&DMA1_Stream1->CR, DMA_SxCR_EN);

// Init trigger timer (48kHz)
register_set(&TIM7->PSC, 0U, 0xFFFFU);
//register_set(&TIM7->ARR, 2494U, 0xFFFFU);
register_set(&TIM7->ARR, 1247U, 0xFFFFU);
register_set(&TIM7->CR2, (0b10 << TIM_CR2_MMS_Pos), TIM_CR2_MMS_Msk);
register_set(&TIM7->CR1, TIM_CR1_ARPE | TIM_CR1_URS, 0x088EU);
TIM7->SR = 0U;
TIM7->CR1 |= TIM_CR1_CEN;

REGISTER_INTERRUPT(BDMA_Channel0_IRQn, BDMA_Channel0_IRQ_Handler, 20U, FAULT_INTERRUPT_RATE_SOUND_DMA)
sai4_init();
NVIC_EnableIRQ(BDMA_Channel0_IRQn);

}
28 changes: 14 additions & 14 deletions board/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -167,21 +167,21 @@ void tick_handler(void) {
}

#ifdef STM32H7
// while((SAI4_Block_B->SR & SAI_xSR_FLVL) != 0U) {
// puth4(SAI4_Block_B->DR); print("\n");
//while((SAI4_Block_A->SR & SAI_xSR_FLVL) != 0U) {
puth4(SAI4_Block_A->DR); print("\n");
//}

// if(rx_buf[0].buf[0] != 0U) {
// print("----\n");
// print("RX BUFS[0]: "); puth4(rx_buf[0].buf[0]); print(" "); puth4(rx_buf[1].buf[0]); print("\n");
// print("RX BUFS[1000]: "); puth4(rx_buf[0].buf[1000]); print(" "); puth4(rx_buf[1].buf[1000]); print("\n");
// // print("TX BUFS[0]: "); puth4(tx_buf[0].buf[0]); print(" "); puth4(tx_buf[1].buf[0]); print("\n");
// print("TIM7: "); puth4(TIM7->CNT); print("\n");
// print("DMA1_S1->NDTR: "); puth(DMA1_Stream1->NDTR); print("\n");
// print("DMA1_S1->CR: "); puth(DMA1_Stream1->CR); print("\n");
// print("DMA1_S1->LISR: "); puth(DMA1->LISR); print("\n");
// print("----\n");
// }

if(rx_buf[0].buf[0] != 0U) {
print("----\n");
print("RX BUFS[0]: "); puth4(rx_buf[0].buf[0]); print(" "); puth4(rx_buf[1].buf[0]); print("\n");
print("RX BUFS[1000]: "); puth4(rx_buf[0].buf[1000]); print(" "); puth4(rx_buf[1].buf[1000]); print("\n");
// print("TX BUFS[0]: "); puth4(tx_buf[0].buf[0]); print(" "); puth4(tx_buf[1].buf[0]); print("\n");
print("TIM7: "); puth4(TIM7->CNT); print("\n");
print("DMA1_S1->NDTR: "); puth(DMA1_Stream1->NDTR); print("\n");
print("DMA1_S1->CR: "); puth(DMA1_Stream1->CR); print("\n");
print("DMA1_S1->LISR: "); puth(DMA1->LISR); print("\n");
print("----\n");
}
#endif

// decimated to 1Hz
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