Simulator compatibility #56
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* Fix analog_io placemnet * [CI] Add workflow for auto-updating caravel-lite * [CI] Silence lvs checks for caravel and GL sim for caravel and qspi * Modified the "caravan" analog project to replace 8 of the 11 power pads being used as placeholders for the analog I/O with the new sky130_ef_io__analog_pad. The remaining 3 pads continue to use sky130_fd_io__top_power_hvc_wpadv2, providing a few clamp circuits that users can connect to additional analog power supplies if they need them. * Apply automatic changes to Manifest and README.rst * Added three user project IRQ lines to input to the management SoC to allow the SoC to respond to triggered events from the user project instead of having to poll for them. * Apply automatic changes to Manifest and README.rst * Modified the GPIO control block to propagate the clock and reset signals. Otherwise, per the existing MPW-one caravel chip, the top-level routing is not generating a clock tree and so creates a long and highly resistive network for clock and reset that will probably cause the clock rate to have to be significantly reduced for the serial load to work. The modification means that the management SoC only drives clock and reset on the first control block on each side. The signal transfer then ripples from the front to the end of each serial chain, mitigating timing issues. * Apply automatic changes to Manifest and README.rst * Additional changes to caravel: (1) Added "input enable" bits for each logic analyzer input from the user project to the management SoC. This allows the user to ignore any bits not being used, and they do not need to be wired out from the user project. (2) Made a simple change to the way the logic analyzer reads inputs, which decouples inputs and outputs. This doubles the number of available logic analyzer bits by allowing simultaneous use of 128 inputs and 128 outputs. (3) Added logic to the management protect block so that the output enable signals work as advertised and put the output into a high-impedence state. Previously it could be used by the user project to selectively multiplex the output, but did not prevent the output from being driven. * Apply automatic changes to Manifest and README.rst * One additional useful function for the logic analyzer, to sample across the entire set of 128 bits, with a simultaneous data capture. * Apply automatic changes to Manifest and README.rst * Update open_pdks and skywater pdk to latest * Add analog wrapper * Apply automatic changes to Manifest and README.rst * Corrected errors in the chip_io_alt layout for caravan, pointed out by Manar Abdelatty, where the references were to sky130_fd_io__analog_pad, which was done before I decided to make the name sky130_ef_io__analog_pad. * Update analog wrapper - fixed placement of io_in_3v3 pins - dropped power straps * Makefile updates - add target for running xor against analog wrapper - change open_pdks url to github for now till opencircuit design is stable * [CI] fix dv script * [CI] Update lvs - dropeed chip_io from CI, needs to be rebuilt with latest pdk - currently fails due to name changes from ef_io -> fd_io * [CI] fix lvs script * [DV] update wb_utests to reflect new changes to LA and mgmt_protect * [CI] Run RTL simulation only for now since GL netlists are obselete * Documentation updates * Apply automatic changes to Manifest and README.rst * [CI] Run DV on every push * [CI] update number of total expected "passes" * Update README.src.rst * Apply automatic changes to Manifest and README.rst * Update wrapper view * Update Makefile * Fix gpio_control_block serial_clock_out definition * Apply automatic changes to Manifest and README.rst * Removed unused gpio_control blocks from caravan. Redrew the user analog project wrapper to maximize area and to bring the power supplies directly into the user core as stub connections. Redrew the analog connections larger to match the pads, and added the clamp connections on the three remaining power pads in the middle. * Modified the analog padframe, wrapper, and caravan harness to better reflect what I need all of them to look like. * Doc updates * Apply automatic changes to Manifest and README.rst * [DATA] Update wrappers views * Update documentation * Apply automatic changes to Manifest and README.rst * Restore mgmt_core.mag.gz * [CI] update caravel-lite Co-authored-by: Tim Edwards <[email protected]> Co-authored-by: RTimothyEdwards <[email protected]> Co-authored-by: Manarabdelaty <[email protected]>
Most files use the Verilog-2001 port declaration style using implicit type declaration.
In cases where the port type must be changed, e.g. an output as reg, it was set in the body of the module (a là Verilog-1995), instead of the header after the direction specification.
E.g. in user_id_programming.v:
```
module user_id_programming #(
..-
) (
output [31:0] mask_rev
);
wire [31:0] mask_rev;
wire [31:0] user_proj_id_high;
wire [31:0] user_proj_id_low;
....
endmodule
```
This seems to be a problem for some simulators, e.g. Modelsim, which think the `wire [31:0] mask_rev;` line declares a new wire. because the name was already used in the scope this results in an error.
Thus such cases where made to use the 2001-style port declaration only.
|
@heavySea Can you run |
|
I will rebase the commits and open a new PR... |
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This Pull Requests has same suggested fixes related to problems during simulation with Modelsim (and probably with others too).
First commit:
Most files use the Verilog-2001 port declaration style using implicit type declaration.
In cases where the port type must be changed, e.g. an output as reg, it was set in the body of the module (à la Verilog-1995), instead of the header after the direction specification.
E.g. in user_id_programming.v:
This seems to be a problem for some simulators, e.g. Modelsim, which think the
wire [31:0] mask_rev;line declares a new wire. Since the name was already used in the scope of the module, this results in an error.Thus, such cases where made to use the 2001-style port declaration only.
Second commit:
Solves #54
Third commit:
Suggested Fix for #55
Note: Both requests do only change syntax / Simulation related parts of the design.