global: Use new WaitTimer integrated cast to int.

litex-hub · Aug 1, 2023 · efc15a9 · efc15a9
1 parent f780b5f
commit efc15a9
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/litex_boards/platforms/qmtech_daughterboard.py b/litex_boards/platforms/qmtech_daughterboard.py
@@ -39,7 +39,7 @@ def __init__(self, segs, sels, sys_clk_freq, period=1e-2):
 
         self.comb += Case(hexa, cases)
 
-        timer = WaitTimer(int(period*sys_clk_freq/(2*n)))
+        timer = WaitTimer(period*sys_clk_freq/(2*n))
         self.submodules += timer
         self.comb += timer.wait.eq(~timer.done)
         self.sync += If(timer.done,

diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py
@@ -65,7 +65,7 @@ def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(int(48e6))
+        reset_timer = WaitTimer(48e6)
         reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
@@ -135,7 +135,7 @@ def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(int(48e6))
+        reset_timer = WaitTimer(48e6)
         reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)