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Add behavior to handle unmapped muxes without constant inputs better #1869

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Motivate of the pull request

  • To address an existing issue. If so, please provide a link to the issue:
  • Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

Which part of the code base require a change

  • VPR
  • Tileable routing architecture generator
  • OpenFPGA libraries
  • FPGA-Verilog
  • FPGA-Bitstream
  • FPGA-SDC
  • FPGA-SPICE
  • Flow scripts
  • Architecture library
  • Cell library
  • Documentation
  • Regression tests
  • Continous Integration (CI) scripts

Impact of the pull request

  • Require a change on Quality of Results (QoR)
  • Break back-compatibility. If so, please list who may be influenced.

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@tangxifan tangxifan left a comment

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@fkosar-ql Thanks for the contribution. Can you add a dedicated testcase?

openfpga/src/base/openfpga_bitstream_template.h Outdated Show resolved Hide resolved
openfpga/src/fpga_bitstream/build_device_bitstream.cpp Outdated Show resolved Hide resolved
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp Outdated Show resolved Hide resolved
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp Outdated Show resolved Hide resolved
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openfpga/src/fpga_bitstream/build_routing_bitstream.cpp Outdated Show resolved Hide resolved
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@fkosar-ql Can you add a testcase, and I can merge this PR.

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@fkosar-ql One more thing. Can you document the mux decoding strategy here: https://openfpga.readthedocs.io/en/master/manual/arch_lang/circuit_model_examples/#cmdoption-arg-2

To the syntax add_const_input, comment on the impact when it is not enabled.

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Thank you.

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3 participants