treewide: Add idma to ethernet

.gitignore

@@ -0,0 +1 @@
+.bender

Bender.lock

@@ -23,8 +23,8 @@ packages:
     dependencies:
     - axi
   axi_stream:
-    revision: 472751f550e3918215603e21734fe0ece3c66f79
-    version: null
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
     source:
       Git: [email protected]:pulp-platform/axi_stream.git
     dependencies:
@@ -43,15 +43,33 @@ packages:
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
+  idma:
+    revision: 18fa40f0b12927622c6a0ff771fb0142d20bcb3d
+    version: null
+    source:
+      Git: [email protected]:pulp-platform/iDMA.git
+    dependencies:
+    - axi
+    - common_cells
+    - common_verification
+    - idma_gen
+    - register_interface
+  idma_gen:
+    revision: null
+    version: null
+    source:
+      Path: .bender/git/checkouts/idma-c23dbd3f440503c0/target/rtl
+    dependencies: []
   register_interface:
-    revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
-    version: 0.3.9
+    revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
+    version: 0.4.2
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
     - common_cells
+    - common_verification
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

Bender.yml

@@ -1,3 +1,7 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
 package:
   name: pulp-ethernet
 
@@ -11,22 +15,25 @@ package:
     - "Davide Rossi <[email protected]>"
 
 dependencies:
-  axi_mem_if : { git: [email protected]:pulp-platform/axi_mem_if.git, version: 0.2.1 }
-  axi : { git: "[email protected]:pulp-platform/axi.git", version: 0.39.1 }
-  common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
-  register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 }
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
-  axi_stream: { git: "[email protected]:pulp-platform/axi_stream.git", rev: "472751f550e3918215603e21734fe0ece3c66f79" }
+  axi : { git: "[email protected]:pulp-platform/axi.git",                                     version: 0.39.1 }
+  axi_mem_if : { git: [email protected]:pulp-platform/axi_mem_if.git,                         version: 0.2.1  }
+  axi_stream: { git: "[email protected]:pulp-platform/axi_stream.git",                        rev: "54891ff"  } # branch: main
+  common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3  }
+  register_interface : { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.2  }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git",                version: 1.32.0 }
+  idma: { git: "[email protected]:pulp-platform/iDMA.git",                                    rev: "18fa40f" } # branch: cl/idma-eth
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
   # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
   # levels 1 and 0, etc. Files within a level are ordered alphabetically.
   # Level 0
-  - gen/eth_framing_reg_pkg.sv
-  - gen/eth_framing_reg_top.sv
+  - gen/eth_idma_reg_pkg.sv
+  - gen/eth_idma_reg_top.sv
   - rtl/axis_gmii_rx.sv
   - rtl/axis_gmii_tx.sv
+  - rtl/fll_dummy.sv
+  - rtl/clk_gen_hyper.sv
   # Level 1
   - rtl/eth_mac_1g_rgmii_fifo.sv
   - rtl/eth_mac_1g_rgmii.sv
@@ -40,9 +47,11 @@ sources:
   - rtl/ssio_ddr_in.sv
   # Level 2
   - rtl/framing_top.sv
-  - rtl/eth_top_pkg.sv
+  - rtl/eth_idma_pkg.sv
   - rtl/eth_top.sv
-  - target/synth/eth_top_synth.sv
+  - rtl/eth_clk_gen.sv
+  - rtl/eth_idma_wrap.sv
+  - target/synth/eth_idma_wrap_synth.sv
 
   - target: test
     files:

README.md

@@ -17,6 +17,12 @@ used.
 `pulp-ethernet` is intended for use with https://github.com/pulp-platform/ariane
 (a RISCV Linux-capable soft core).
 
+## Generate iDMA with AXIS support  (Terminal)
+
+```
+make eth-gen
+```
+
 ## Compile (Questa)
 
 ```

eth.mk

@@ -17,10 +17,13 @@
 BENDER ?= bender
 QUESTA ?= questa-2022.3
 TBENCH ?= eth_tb
-DUT    ?= eth_rgmii_synth
+DUT    ?= eth_idma_wrap
 
 # Design and simulation variables
 ETH_ROOT      ?= $(shell $(BENDER) path fe-ethernet)
+ETH_VSIM_DIR  := $(ETH_ROOT)/target/sim/vsim
+
+IDMA_ROOT     ?= $(shell $(BENDER) path idma)
 
 QUESTA_FLAGS := -permissive -suppress 3009 -suppress 8386 -error 7 +UVM_NO_RELNOTES
 #QUESTA_FLAGS :=
@@ -34,6 +37,16 @@ else
 	RUN_AND_EXIT := run -all; exit
 endif
 
+########
+# Deps #
+########
+
+eth-checkout:
+	$(BENDER) checkout
+	touch Bender.lock
+
+include $(IDMA_ROOT)/idma.mk
+
 ######################
 # Nonfree components #
 ######################
@@ -47,31 +60,46 @@ eth-nonfree-init:
 
 -include $(ETH_ROOT)/nonfree/nonfree.mk
 
+##############
+# HW GEN     #
+##############
+
+eth-idma-gen: eth-checkout
+	make -C $(IDMA_ROOT) idma_hw_all
+
 ##############
 # Simulation #
 ##############
 
+# Questasim
 $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl: Bender.yml
-	$(BENDER) script vsim -t test \
+	$(BENDER) script vsim -t rtl -t test -t sim \
 	--vlog-arg="-svinputport=compat" \
 	--vlog-arg="-override_timescale 1ns/1ps" \
 	--vlog-arg="-suppress 2583" > $@
 	echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@
 
-eth-sim-init: $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl
-
-eth-hw-build: eth-sim-init
-	$(QUESTA) vsim -c -do "quit -code [source $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl]"
+eth-vsim-sim-build: eth-sim-init
+	cd $(ETH_VSIM_DIR) && $(QUESTA) vsim -c -do "quit -code [source $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl]"
 
-eth-hw-sim:
-	$(QUESTA) vsim $(VSIM_FLAGS) -do \
+eth-vsim-sim-run:
+	cd $(ETH_VSIM_DIR) && $(QUESTA) vsim $(VSIM_FLAGS) -do \
 		"set TESTBENCH $(TBENCH); \
 		 set VSIM_FLAGS \"$(VSIM_FLAGS)\"; \
 		 source $(ETH_ROOT)/target/sim/vsim/start.eth.tcl ; \
 		 $(RUN_AND_EXIT)"
 
+eth-vsim-sim-clean:
+	cd $(ETH_VSIM_DIR) && rm -rf work transcript
+
+# Global targets
+
+eth-sim-init: $(ETH_ROOT)/target/sim/vsim/compile.eth.tcl
+eth-sim-build: eth-vsim-sim-build
+eth-sim-clean: eth-vsim-sim-clean
+
 #################################
 # Phonies (KEEP AT END OF FILE) #
 #################################
 
-.PHONY: eth-all eth-nonfree-init eth-sim-init eth-hw-build eth-hw-sim
+.PHONY: eth-all eth-nonfree-init eth-checkout eth-idma-gen eth-sim-init eth-sim-build eth-sim-clean eth-vsim-sim-build eth-vsim-sim-clean eth-vsim-sim-run

gen/Makefile

@@ -18,18 +18,18 @@
 
 REGTOOL ?= regtool.py
 
-SRCS = eth_framing_reg_top.sv eth_framing_reg_pkg.sv
+SRCS = eth_idma_reg_top.sv eth_idma_reg_pkg.sv
 
 all: srcs headers
 
 srcs: $(SRCS)
 
-eth_framing_reg_top.sv: eth_framing_regs.hjson
+eth_idma_reg_top.sv: eth_idma_reg.hjson
 	$(REGTOOL) -r $< -t .
 
-headers: eth_framing.h
+headers: eth_idma_reg.h
 
-eth_framing.h: eth_framing_regs.hjson
+eth_idma_reg.h: eth_idma_reg.hjson
 	$(REGTOOL) --cdefines $< > $@
 
 .PHONY: install