treewide: Mixed fixes

Bender.lock

@@ -44,7 +44,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   idma:
-    revision: 18fa40f0b12927622c6a0ff771fb0142d20bcb3d
+    revision: a80fcace92b1562e7cd76c8615298b5623ba74d2
     version: null
     source:
       Git: [email protected]:pulp-platform/iDMA.git

Bender.yml

@@ -21,7 +21,7 @@ dependencies:
   common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3  }
   register_interface : { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.2  }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git",                version: 1.32.0 }
-  idma: { git: "[email protected]:pulp-platform/iDMA.git",                                    rev: "18fa40f" } # branch: cl/idma-eth
+  idma: { git: "[email protected]:pulp-platform/iDMA.git",                                    rev: "a80fcace" } # branch: cl/idma-eth
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -51,7 +51,10 @@ sources:
   - rtl/eth_top.sv
   - rtl/eth_clk_gen.sv
   - rtl/eth_idma_wrap.sv
-  - target/synth/eth_idma_wrap_synth.sv
+
+  - target: any(synthesis, asic)
+    files:
+      - target/synth/eth_idma_wrap_synth.sv
 
   - target: test
     files:

eth.mk

@@ -52,7 +52,7 @@ include $(IDMA_ROOT)/idma.mk
 ######################
 
 ETH_NONFREE_REMOTE ?= [email protected]:pulp-restricted/pulp-ethernet-nonfree.git
-ETH_NONFREE_COMMIT ?= cd8dcd3
+ETH_NONFREE_COMMIT ?= 5633df7
 
 eth-nonfree-init:
 	git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree

rtl/eth_clk_gen.sv

@@ -15,7 +15,9 @@ module eth_clk_gen (
 logic clk_eth_125;
 assign clk_eth_125 = clk_eth_125_o;
 
-fll_dummy i_gf12_fll (         // Clock & reset
+fll_dummy #(
+  .NB_FLL (1)
+) i_gf12_fll (         // Clock & reset
   .OUTCLK ( clk_eth_125_o  ), // FLL clock outputs
   .REFCLK ( ref_clk_i      ), // Reference clock input
   .RSTB   ( rst_ni         ), // Asynchronous reset (active low)
@@ -44,4 +46,4 @@ clk_gen_hyper i_clk_gen_ethernet (
   .clk270_o (                   )
 );
 
-endmodule : eth_clk_gen
+endmodule : eth_clk_gen

rtl/eth_idma_pkg.sv

@@ -24,7 +24,7 @@ package eth_idma_pkg;
   `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t)
 
   parameter int unsigned DataWidth           = 64;
-  parameter int unsigned AddrWidth           = 64;
+  parameter int unsigned AddrWidth           = 32;
   parameter int unsigned UserWidth           = 1;
   parameter int unsigned AxiIdWidth          = 5;
   parameter int unsigned TFLenWidth          = 32;
@@ -33,70 +33,70 @@ package eth_idma_pkg;
   localparam int unsigned OffsetWidth   = $clog2(StrbWidth);
 
   typedef logic [AddrWidth-1:0]   addr_t;
-  typedef logic [AxiIdWidth-1:0]   id_t;
+  typedef logic [AxiIdWidth-1:0]  id_t;
   typedef logic [UserWidth-1:0]   user_t;
   typedef logic [StrbWidth-1:0]   strb_t;
   typedef logic [DataWidth-1:0]   data_t;
   typedef logic [TFLenWidth-1:0]  tf_len_t;
 
- /// AXI4+ATOP typedefs
- `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t)
- `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t)
- `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t)
-
- `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t)
- `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t)
-
- `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t)
- `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t)
-
- /// AXI Stream typedefs
- `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
- `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t)
- `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t)
-
- /// Meta Channel Widths
- localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth);
- localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth);
- localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t);
-
- `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t)
- `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t)
- `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t)
- `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t)
-
- function int unsigned max_width(input int unsigned a, b);
-     return (a > b) ? a : b;
- endfunction
-
-typedef struct packed {
-    axi_ar_chan_t ar_chan;
-    logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding;
-} axi_read_ar_chan_padded_t;
-
-typedef struct packed {
-    axis_t_chan_t t_chan;
-    logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding;
-} axis_read_t_chan_padded_t;
-
-typedef union packed {
-    axi_read_ar_chan_padded_t axi;
-    axis_read_t_chan_padded_t axis;
-} read_meta_channel_t;
-
-typedef struct packed {
-    axi_aw_chan_t aw_chan;
-    logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding;
-} axi_write_aw_chan_padded_t;
-
-typedef struct packed {
-    axis_t_chan_t t_chan;
-    logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding;
-} axis_write_t_chan_padded_t;
-
-typedef union packed {
-    axi_write_aw_chan_padded_t axi;
-    axis_write_t_chan_padded_t axis;
-} write_meta_channel_t;
+  /// AXI4+ATOP typedefs
+  `AXI_TYPEDEF_AW_CHAN_T(axi_aw_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_W_CHAN_T(axi_w_chan_t, data_t, strb_t, user_t)
+  `AXI_TYPEDEF_B_CHAN_T(axi_b_chan_t, id_t, user_t)
+  
+  `AXI_TYPEDEF_AR_CHAN_T(axi_ar_chan_t, addr_t, id_t, user_t)
+  `AXI_TYPEDEF_R_CHAN_T(axi_r_chan_t, data_t, id_t, user_t)
+  
+  `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t)
+  `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t)
+  
+  /// AXI Stream typedefs
+  `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
+  `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axis_t_chan_t)
+  `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t)
+  
+  /// Meta Channel Widths
+  localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth);
+  localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth);
+  localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t);
+  
+  `IDMA_TYPEDEF_OPTIONS_T(options_t, id_t)
+  `IDMA_TYPEDEF_REQ_T(idma_req_t, tf_len_t, addr_t, options_t)
+  `IDMA_TYPEDEF_ERR_PAYLOAD_T(err_payload_t, addr_t)
+  `IDMA_TYPEDEF_RSP_T(idma_rsp_t, err_payload_t)
+  
+  function automatic int unsigned max_width(input int unsigned a, b);
+      return (a > b) ? a : b;
+  endfunction
+  
+  typedef struct packed {
+      axi_ar_chan_t ar_chan;
+      logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axi_ar_chan_width:0] padding;
+  } axi_read_ar_chan_padded_t;
+  
+  typedef struct packed {
+      axis_t_chan_t t_chan;
+      logic[max_width(axi_ar_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding;
+  } axis_read_t_chan_padded_t;
+  
+  typedef union packed {
+      axi_read_ar_chan_padded_t axi;
+      axis_read_t_chan_padded_t axis;
+  } read_meta_channel_t;
+  
+  typedef struct packed {
+      axi_aw_chan_t aw_chan;
+      logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axi_aw_chan_width:0] padding;
+  } axi_write_aw_chan_padded_t;
+  
+  typedef struct packed {
+      axis_t_chan_t t_chan;
+      logic[max_width(axi_aw_chan_width, axis_t_chan_width)-axis_t_chan_width:0] padding;
+  } axis_write_t_chan_padded_t;
+  
+  typedef union packed {
+      axi_write_aw_chan_padded_t axi;
+      axis_write_t_chan_padded_t axis;
+  } write_meta_channel_t;
 
 endpackage : eth_idma_pkg

rtl/eth_idma_wrap.sv

@@ -15,13 +15,13 @@
 
 module eth_idma_wrap #(
   /// Data width
-  parameter int unsigned DataWidth           = 32'd32,
+  parameter int unsigned DataWidth           = 32'd64,
   /// Address width
   parameter int unsigned AddrWidth           = 32'd32,
   /// AXI User width
   parameter int unsigned UserWidth           = 32'd1,
   /// AXI ID width
-  parameter int unsigned AxiIdWidth          = 32'd1,
+  parameter int unsigned AxiIdWidth          = 32'd5,
   /// Number of transaction that can be in-flight concurrently
   parameter int unsigned NumAxInFlight       = 32'd3,
   /// The depth of the internal reorder buffer

target/synth/eth_idma_wrap_synth.sv

@@ -14,13 +14,13 @@
 
 module eth_idma_wrap_synth #(
   /// Data width
-  parameter int unsigned DataWidth           = 32'd32,
+  parameter int unsigned DataWidth           = 32'd64,
   /// Address width
   parameter int unsigned AddrWidth           = 32'd32,
   /// AXI User width
   parameter int unsigned UserWidth           = 32'd1,
   /// AXI ID width
-  parameter int unsigned AxiIdWidth          = 32'd1,
+  parameter int unsigned AxiIdWidth          = 32'd5,
   /// Number of transaction that can be in-flight concurrently
   parameter int unsigned NumAxInFlight       = 32'd3,
   /// The depth of the internal reorder buffer