Add support for Zilsd and Zcmlsd extension

riscv_ctg/constants.py

@@ -191,7 +191,7 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 # increment each value in dataset, increment each value in dataset, add them to the dataset
     return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0
 
-template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"]
+template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml","zilsd.yaml"]
 
 template_files = [os.path.join(root,"data/"+f) for f in template_fnames]
 

riscv_ctg/data/template.yaml

@@ -6,7 +6,10 @@ metadata:
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
-
+  pair_regs_zcmlsd: &pair_regs_zcmlsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(0,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  c_pair_regs: &c_pair_regs "['x'+str(x) for x in range(8,16,2)]"
+
 aes32dsi:
   sig:
     stride: 1

riscv_ctg/data/zilsd.yaml

@@ -0,0 +1,128 @@
+# See https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details
+ldz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *pair_regs_zilsd
+  rd_hi: 0
+  isa: 
+    - IZilsd
+  xlen: [32]
+  opcode: ld
+  std_op:
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode:$opcode op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align;rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,ld,$ea_align)
+
+sdz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *pair_regs_zilsd
+  rd_op_data: *all_regs
+  rs2_hi: 0
+  xlen: [32]
+  opcode: sd
+  std_op:
+  isa: 
+    - IZilsd
+  formattype: 'szformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$opcode; op1:$rs1; op2:$rs2; op2val:$rs2_val;op3val:$rs2_hi_val; immval:$imm_val; align:$ea_align; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,sd,$ea_align)
+
+c.ldz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_pair_regs 
+  rd_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zcmlsd
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,c.ld,$rs1_val)
+
+c.ldspz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rd_op_data: *pair_regs_zcmlsd
+  rd_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zcmlsd
+  formattype: 'ciformat'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; rd_hi:$rd_hi
+    TEST_LOAD_ZILSD($swreg,$testreg,$index,x2,$rd,$rd_hi,$imm_val,$offset,c.ldsp,0)
+
+c.sdz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_pair_regs
+  rs2_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zcmlsd
+  formattype: 'cszformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; op3val:$rs2_hi_val; $immval:$imm_val; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sd,0)
+
+c.sdspz:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  rs2_op_data: *pair_regs_zilsd
+  rs2_hi: 0
+  xlen: [32]
+  std_op:
+  isa: 
+    - ICZilsd_Zcmlsd
+  formattype: 'csszformat'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  rs2_hi_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val;  op3val:$rs2_hi_val; immval:$imm_val; rs2_hi:$rs2_hi
+    TEST_STORE_ZILSD($swreg,$testreg,$index,x2,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sdsp,0)

riscv_ctg/dsp_function.py

@@ -151,6 +151,12 @@ def incr_reg_num(reg):
     num = num + 1
     return name + str(num)
 
+def dec_reg_num(reg):
+    name = reg[0]
+    num = int(reg[1:])
+    num = num - 2
+    return name + str(num)
+
 def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
     '''
     This function generate high registers for paired register operands, rs1_hi, rs2_hi and rd_hi depending on the specification of the p64_profile string.

riscv_ctg/env/arch_test.h

@@ -961,6 +961,25 @@ nop
 csrr flagreg, fcsr                                                                      ;\
 RVTEST_SIGUPD_F(swreg,destreg,flagreg) 
 
+//Zilsd and Zcmlsd instruction
+#define TEST_LOAD_ZILSD(swreg,testreg,index,rs1,destreg,rd_hi,imm_val,offset,inst,adj);\
+LA(rs1,rvtest_data+(index*4)+adj-imm_val);\
+inst destreg, imm_val(rs1)      ;\
+nop                 ;\
+nop                 ;\
+RVTEST_SIGUPD(swreg,destreg) ;\
+RVTEST_SIGUPD(swreg,rd_hi)
+
+#define TEST_STORE_ZILSD(swreg,testreg,index,rs1,rs2,rs2_hi,rs2_val,rs2_hi_val,imm_val,offset,inst,adj) ;\
+LI(rs2,rs2_val)             ;\
+LI(rs2_hi,rs2_hi_val)             ;\
+addi rs1,swreg,offset+adj       ;\
+LI(testreg,imm_val)         ;\
+sub rs1,rs1,testreg         ;\
+inst rs2, imm_val(rs1)          ;\
+nop                 ;\
+nop
+
 #define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \
     LI(TEMP_REG,VAL);\
     and TEMP_REG,TEMP_REG,MASK_REG;\

riscv_ctg/generator.py

@@ -36,6 +36,8 @@
 one_operand_dinstructions += ["fround.d", "froundnx.d"]
 two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"]
 
+#Zilsd
+zilsd_instructions = ["ldz","sdz","c.ldz","c.sdz","c.ldspz","c.sdspz"]
 
 def is_fp_instruction(insn):
     '''
@@ -71,6 +73,7 @@ def get_rm(opcode):
     'r4format': ['rs1', 'rs2', 'rs3', 'rd'],
     'iformat': ['rs1', 'rd'],
     'sformat': ['rs1', 'rs2'],
+    'szformat': ['rs1', 'rs2'],
     'bsformat': ['rs1', 'rs2', 'rd'],
     'bformat': ['rs1', 'rs2'],
     'uformat': ['rd'],
@@ -79,9 +82,11 @@ def get_rm(opcode):
     'cmvformat': ['rd', 'rs2'],
     'ciformat': ['rd'],
     'cssformat': ['rs2'],
+    'csszformat': ['rs2'],
     'ciwformat': ['rd'],
     'clformat': ['rs1', 'rd'],
     'csformat': ['rs1', 'rs2'],
+    'cszformat': ['rs1', 'rs2'],
     'caformat': ['rs1', 'rs2'],
     'cuformat': ['rs1'],
     'cbformat': ['rs1'],
@@ -126,6 +131,7 @@ def get_rm(opcode):
         (['rs{0}_sgn_prefix'.format(x) for x in range(1,4)] if is_sgn_extd else [])",
     'iformat': "['rs1_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])",
     'sformat': "['rs1_val', 'rs2_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])",
+    'szformat': "['rs1_val', 'rs2_val', 'rs2_hi_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])",
     'bsformat': "['rs1_val', 'rs2_val', 'imm_val']",
     'bformat': "['rs1_val', 'rs2_val', 'imm_val']",
     'uformat': "['imm_val']",
@@ -134,6 +140,7 @@ def get_rm(opcode):
     'cmvformat': "['rs2_val']",
     'ciformat': "['rs1_val', 'imm_val']",
     'cssformat': "['rs2_val', 'imm_val']",
+    'csszformat': "['rs2_val', 'rs2_hi_val', 'imm_val']",
     'ciwformat': "['imm_val']",
     'clformat': "['rs1_val', 'imm_val', 'fcsr']",
     'cuformat': "['rs1_val']",
@@ -142,6 +149,7 @@ def get_rm(opcode):
     'csbformat': "['rs1_val','rs2_val','imm_val']",
     'cshformat': "['rs1_val','rs2_val','imm_val']",
     'csformat': "['rs1_val', 'rs2_val', 'imm_val']",
+    'cszformat': "['rs1_val', 'rs2_val', 'rs2_hi_val', 'imm_val']",
     'caformat': "['rs1_val', 'rs2_val']",
     'cbformat': "['rs1_val', 'imm_val']",
     'cjformat': "['imm_val']",
@@ -281,7 +289,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx
         self.inxFlag = inxFlag
         self.is_sgn_extd = is_sgn_extd
 
-        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw"]:
+        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","ldz","sdz"]:
             self.val_vars = self.val_vars + ['ea_align']
         self.template = opnode['template']
         self.opnode = opnode
@@ -818,7 +826,7 @@ def gen_inst(self,op_comb, val_comb, cgf):
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez']:
                 instr_dict.append(self.__cb_instr__(op,val))
-            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']:
+            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.ldspz','c.sdspz']:
                 if any([x == 'x2' for x in op]):
                     cont.append(val)
                 instr_dict.append(self.__cmemsp_instr__(op,val))
@@ -838,7 +846,7 @@ def gen_inst(self,op_comb, val_comb, cgf):
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez','c.lbu','c.lhu','c.lh','c.sb','c.sh']:
                 instr_dict.append(self.__cb_instr__(op,val))
-            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']:
+            elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.ldspz','c.sdspz']:
                 instr_dict.append(self.__cmemsp_instr__(op,val))
             elif self.fmt == 'bformat' or self.opcode in ['c.j']:
                 instr_dict.append(self.__bfmt_instr__(op,val))
@@ -923,7 +931,7 @@ def eval_inst_coverage(coverpoints,instr):
         for instr in instr_dict:
             unique = False
             skip_val = False
-            if instr['inst'] in cgf['mnemonics']:
+            if instr['inst'] in cgf['mnemonics'] or instr['inst'] in zilsd_instructions:
                 if 'rs1' in instr and 'rs2' in instr:
                     if instr['rs1'] == instr['rs2']:
                         skip_val = True
@@ -948,6 +956,14 @@ def eval_inst_coverage(coverpoints,instr):
                     final_instr.append(instr)
                 else:
                     i+=1
+            if instr['inst'] in zilsd_instructions:
+                if 'rs2_hi' and 'rd' not in instr :
+                    instr.update({'rs2_hi': incr_reg_num(instr['rs2'])})
+                    if instr['rs2_hi'] == instr['rs1'] and instr['rs1'] == 'x31':
+                            instr.update({'rs1': dec_reg_num(instr['rs1'])})
+                elif 'rd_hi' not in instr and 'rd' in instr:
+                    instr.update({'rd_hi': incr_reg_num(instr['rd'])})
+
 
         if any('IP' in isa for isa in self.opnode['isa']):
             if 'p64_profile' in self.opnode:

sample_cgfs/dataset.cgf

@@ -171,6 +171,24 @@ datasets:
     x28: 0
     x30: 0
 
+  pair_regs_zilsd: &pair_regs_zilsd
+    x0: 0
+    x2: 0
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   c_regs: &c_regs
     x8: 0
     x9: 0
@@ -246,6 +264,28 @@ datasets:
     x30: 0
     x31: 0
 
+  c_pair_regs: &c_pair_regs
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+
+  c_pair_regs_mx2: &c_pair_regs_mx2
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   cbfmt_immval_sgn: &cbfmt_immval_sgn
     'imm_val == (-2**(6-1))': 0
     'imm_val == 0': 0