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Releases: chipsalliance/python-fpga-interchange

v0.0.20

23 Sep 15:49
@tmichalak tmichalak
v0.0.20
bd3d5d1
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v0.0.20 Latest
Latest

Turn off pseudoPIPs going through LUT6 bels in Xilinx 7-series

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Macro Clusters

23 Sep 12:55
@tmichalak tmichalak
v0.0.19
7a9d020
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Macro Clusters

Add converting macros to clusters.

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v0.0.7: Merge pull request #48 from litghost/add_lut_output_pin

01 Apr 22:25
@litghost litghost
v0.0.7
28c32ec
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v0.0.7: Merge pull request #48 from litghost/add_lut_output_pin Pre-release
Pre-release 
Add LUT output pins to chipdb.
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v0.0.6: Merge pull request #46 from litghost/set_default_parameters

29 Mar 17:27
@litghost litghost
v0.0.6
b4331ef
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v0.0.6: Merge pull request #46 from litghost/set_default_parameters Pre-release
Pre-release 
Set default parameters on logical netlists from Yosys JSON.
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v0.0.5: Merge pull request #43 from gatecat/nexus_device_stub

25 Mar 15:37
@litghost litghost
v0.0.5
5f5330d
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v0.0.5: Merge pull request #43 from gatecat/nexus_device_stub Pre-release
Pre-release 
nexus: Add stub device_config.yaml
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